Searched refs:FP_X_INV (Results 1 - 25 of 34) sorted by relevance

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/netbsd-current/sys/arch/alpha/include/
H A Dieeefp.h30 #define FP_AA_FLAGS (FP_X_INV | FP_X_DZ | FP_X_OFL | FP_X_UFL | FP_X_IMP)
37 #define float_set_invalid() float_raise(FP_X_INV)
42 #define FP_X_INV FE_INVALID /* invalid operation exception */ macro
/netbsd-current/sys/arch/or1k/include/
H A Dieeefp.h25 #define FP_X_INV FE_INVALID /* invalid operation exception */ macro
/netbsd-current/sys/arch/sh3/include/
H A Dieeefp.h25 #define FP_X_INV FE_INVALID /* invalid operation exception */ macro
42 #define FP_X_INV 0x01 /* invalid operation exception */ macro
67 __fp |= FP_X_INV;
84 if (__fp & FP_X_INV)
/netbsd-current/sys/arch/sparc/include/
H A Dieeefp.h21 #define FP_X_INV 0x10 /* invalid operation exception */ macro
/netbsd-current/sys/arch/hppa/include/
H A Dieeefp.h18 #define FP_X_INV 0x10 /* invalid operation exception */ macro
/netbsd-current/sys/arch/riscv/include/
H A Dieeefp.h25 #define FP_X_INV FE_INVALID /* invalid operation exception */ macro
/netbsd-current/sys/arch/x86/include/
H A Dieeefp.h15 #define FP_X_INV FE_INVALID /* invalid operation exception */ macro
/netbsd-current/sys/arch/ia64/include/
H A Dieeefp.h33 #define FP_X_INV FE_INVALID /* invalid operation exception */ macro
/netbsd-current/external/gpl3/gcc.old/dist/libgfortran/config/
H A Dfpu-sysv.h61 #ifdef FP_X_INV
63 cw |= FP_X_INV;
65 cw &= ~FP_X_INV;
113 #ifdef FP_X_INV
114 if (cw & FP_X_INV) res |= GFC_FPE_INVALID;
151 #ifndef FP_X_INV
200 #ifdef FP_X_INV
201 if (set_excepts & FP_X_INV)
241 #ifdef FP_X_INV
243 flags |= FP_X_INV;
[all...]
/netbsd-current/external/gpl3/gcc/dist/libgfortran/config/
H A Dfpu-sysv.h61 #ifdef FP_X_INV
63 cw |= FP_X_INV;
65 cw &= ~FP_X_INV;
113 #ifdef FP_X_INV
114 if (cw & FP_X_INV) res |= GFC_FPE_INVALID;
151 #ifndef FP_X_INV
200 #ifdef FP_X_INV
201 if (set_excepts & FP_X_INV)
241 #ifdef FP_X_INV
243 flags |= FP_X_INV;
[all...]
/netbsd-current/sys/arch/powerpc/include/
H A Dieeefp.h31 #define FP_X_INV __FPE(FE_INVALID) /* invalid operation exception */ macro
/netbsd-current/sys/arch/mips/include/
H A Dieeefp.h31 #define FP_X_INV __FPE(FE_INVALID) /* invalid operation exception */ macro
/netbsd-current/sys/arch/arm/include/
H A Dieeefp.h31 #define FP_X_INV FE_INVALID /* invalid operation exception */ macro
/netbsd-current/lib/libc/arch/powerpc64/gen/
H A Dfpsetsticky.c62 * FPSCR_VX (aka FP_X_INV) is not a sticky bit but a summary of the
63 * all the FPSCR_VX* sticky bits. So when FP_X_INV is cleared then
66 if ((mask & FP_X_INV) == 0)
/netbsd-current/sys/arch/m68k/include/
H A Dieeefp.h32 #define FP_X_INV __FPE(FE_INVALID) /* invalid operation exception */ macro
/netbsd-current/tests/lib/libc/gen/
H A Dt_fpsetmask.c69 if (0 == fpsetmask(fpsetmask(FP_X_INV))) \
204 { f_inv, FP_X_INV, FPE_FLTINV },
212 { d_inv, FP_X_INV, FPE_FLTINV },
220 { ld_inv, FP_X_INV, FPE_FLTINV },
345 fp_except_t msk, lst[] = { FP_X_INV, FP_X_DZ, FP_X_OFL, FP_X_UFL };
H A Dt_siginfo.c319 if (0 == fpsetmask(fpsetmask(FP_X_INV)))
332 fpsetmask(FP_X_INV|FP_X_DZ|FP_X_OFL|FP_X_UFL|FP_X_IMP);
383 fpsetmask(FP_X_INV|FP_X_DZ|FP_X_OFL|FP_X_UFL|FP_X_IMP);
/netbsd-current/tests/lib/libm/
H A Dt_fenv.c61 if (0 == fpsetmask(fpsetmask(FP_X_INV))) \
275 fpsetmask(FP_X_INV|FP_X_DZ|FP_X_OFL|FP_X_UFL|FP_X_IMP);
279 fpsetmask(FP_X_INV);
348 ATF_CHECK_EQ_MSG(fpgetmask(), FP_X_INV, local
349 "fpgetmask()=%d FP_X_INV=%d",
350 (int)fpgetmask(), (int)FP_X_INV);
/netbsd-current/lib/libc/arch/or1k/gen/
H A Dfpsetsticky.c65 * FPSCR_VX (aka FP_X_INV) is not a sticky bit but a summary of the
66 * all the FPSCR_VX* sticky bits. So when FP_X_INV is cleared then
69 if ((mask & FP_X_INV) == 0)
/netbsd-current/lib/libc/arch/powerpc/gen/
H A Dfpsetsticky.c65 * FPSCR_VX (aka FP_X_INV) is not a sticky bit but a summary of the
66 * all the FPSCR_VX* sticky bits. So when FP_X_INV is cleared then
69 if ((mask & FP_X_INV) == 0)
/netbsd-current/tests/kernel/
H A Dh_segv.c120 if (0 == fpsetmask(fpsetmask(FP_X_INV))) {
/netbsd-current/sys/arch/alpha/alpha/
H A Dfp_complete.c59 __CTASSERT(ALPHA_AESR_INV == (FP_X_INV << 1));
66 __CTASSERT(IEEE_TRAP_ENABLE_INV == (FP_X_INV << 1));
76 __CTASSERT((uint64_t)FP_X_INV << (49 - 0) == FPCR_INVD);
392 fpcr |= (disables & (FP_X_OFL | FP_X_DZ | FP_X_INV)) << (49 - 0);
578 float_raise(FP_X_INV);
/netbsd-current/lib/libc/arch/arm/softfloat/
H A Dsoftfloat.h105 float_flag_invalid = FP_X_INV
/netbsd-current/lib/libc/arch/m68k/softfloat/
H A Dsoftfloat.h106 float_flag_invalid = FP_X_INV
/netbsd-current/lib/libc/arch/mips/softfloat/
H A Dsoftfloat.h106 float_flag_invalid = FP_X_INV

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