Searched refs:ETH_TSR_BNQ (Results 1 - 4 of 4) sorted by relevance

/netbsd-current/sys/arch/arm/at91/
H A Dat91emacreg.h131 #define ETH_TSR_BNQ 0x10U /* 1 = transmit buffer not queued */ macro
H A Dat91emac.c153 EMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ
185 if (!(tsr & ETH_TSR_BNQ)) {
346 EMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ
742 EMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ
/netbsd-current/sys/dev/cadence/
H A Dcemacreg.h183 #define ETH_TSR_BNQ 0x10U /* 1 = transmit buffer not queued (at91rm9200 only) */ macro
H A Dif_cemac.c202 CEMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ
234 if (!(tsr & ETH_TSR_BNQ))
432 CEMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ
951 CEMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ

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