Searched refs:ETH_CTL_RE (Results 1 - 4 of 4) sorted by relevance
| /netbsd-current/sys/arch/arm/at91/ |
| H A D | at91emacreg.h | 91 #define ETH_CTL_RE 0x004U /* 1 = receive enable */ macro
|
| H A D | at91emac.c | 241 EMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE); // disable receiver
243 EMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE); // re-enable receiver
480 EMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR
717 EMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR
771 EMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE);
871 EMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE);
|
| /netbsd-current/sys/dev/cadence/ |
| H A D | if_cemac.c | 303 CEMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE); // disable receiver
305 CEMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE); // re-enable receiver
592 CEMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR
922 CEMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR
981 CEMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE);
1082 CEMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE);
|
| H A D | cemacreg.h | 133 #define ETH_CTL_RE 0x004U /* 1 = receive enable */ macro
|
Completed in 107 milliseconds