Searched refs:DstMO (Results 1 - 8 of 8) sorted by relevance

/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCVSXCopy.cpp91 MachineOperand &DstMO = MI.getOperand(0); local
94 if ( IsVSReg(DstMO.getReg(), MRI) &&
115 } else if (!IsVSReg(DstMO.getReg(), MRI) &&
121 assert((IsF8Reg(DstMO.getReg(), MRI) ||
122 IsVSFReg(DstMO.getReg(), MRI) ||
123 IsVSSReg(DstMO.getReg(), MRI)) &&
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86LowerTileCopy.cpp83 MachineOperand &DstMO = MI.getOperand(0); local
86 Register DstReg = DstMO.getReg();
/netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DExpandPostRAPseudos.cpp144 MachineOperand &DstMO = MI->getOperand(0); local
147 bool IdentityCopy = (SrcMO.getReg() == DstMO.getReg());
167 DstMO.getReg(), SrcMO.getReg(), SrcMO.isKill());
H A DMachineSink.cpp1042 const MachineOperand *SrcMO = nullptr, *DstMO = nullptr; local
1047 DstMO = CopyOperands->Destination;
1067 DbgMO.getSubReg() != DstMO->getSubReg())
1073 if (PostRA && Reg != DstMO->getReg())
H A DTwoAddressInstructionPass.cpp1328 MachineOperand &DstMO = MI->getOperand(DstIdx); local
1330 Register DstReg = DstMO.getReg();
1338 if (SrcMO.isUndef() && !DstMO.getSubReg()) {
1374 const MachineOperand &DstMO = MI->getOperand(DstIdx); local
1375 Register RegA = DstMO.getReg();
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZShortenInst.cpp180 MachineOperand &DstMO = MI.getOperand(0); local
184 if (SystemZMC::getFirstReg(DstMO.getReg()) < 16 &&
188 DstMO.getReg() == AccMO.getReg()) {
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64LoadStoreOptimizer.cpp1038 MachineOperand &DstMO = MIB->getOperand(SExtIdx);
1039 // Right now, DstMO has the extended register, since it comes from an
1041 Register DstRegX = DstMO.getReg();
1045 DstMO.setReg(DstRegW);
H A DAArch64InstrInfo.cpp4139 const MachineOperand &DstMO = MI.getOperand(0);
4141 Register DstReg = DstMO.getReg();
4150 if (DstMO.getSubReg() == 0 && SrcMO.getSubReg() == 0) {
4172 if (IsSpill && DstMO.isUndef() && Register::isPhysicalRegister(SrcReg)) {
4177 switch (DstMO.getSubReg()) {
4219 if (IsFill && SrcMO.getSubReg() == 0 && DstMO.isUndef()) {
4221 switch (DstMO.getSubReg()) {
4244 LoadDst.setSubReg(DstMO.getSubReg());

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