Searched refs:DPM_TABLE_52__VddciLevel_0_Voltage_MASK (Results 1 - 3 of 3) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/smu/
H A Dsmu_7_1_1_sh_mask.h1617 #define DPM_TABLE_52__VddciLevel_0_Voltage_MASK 0xffff0000 macro
H A Dsmu_7_1_0_sh_mask.h971 #define DPM_TABLE_52__VddciLevel_0_Voltage_MASK 0xffff0000 macro
H A Dsmu_7_0_1_sh_mask.h973 #define DPM_TABLE_52__VddciLevel_0_Voltage_MASK 0xffff0000 macro

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