Searched refs:DPM_TABLE_47__VddcLevel_5_padding__SHIFT (Results 1 - 3 of 3) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/smu/
H A Dsmu_7_1_1_sh_mask.h1590 #define DPM_TABLE_47__VddcLevel_5_padding__SHIFT 0x0 macro
H A Dsmu_7_1_0_sh_mask.h944 #define DPM_TABLE_47__VddcLevel_5_padding__SHIFT 0x0 macro
H A Dsmu_7_0_1_sh_mask.h946 #define DPM_TABLE_47__VddcLevel_5_padding__SHIFT 0x0 macro

Completed in 222 milliseconds