Searched refs:DPM_TABLE_43__VddcLevel_3_padding__SHIFT (Results 1 - 3 of 3) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/smu/
H A Dsmu_7_1_1_sh_mask.h1570 #define DPM_TABLE_43__VddcLevel_3_padding__SHIFT 0x0 macro
H A Dsmu_7_1_0_sh_mask.h924 #define DPM_TABLE_43__VddcLevel_3_padding__SHIFT 0x0 macro
H A Dsmu_7_0_1_sh_mask.h926 #define DPM_TABLE_43__VddcLevel_3_padding__SHIFT 0x0 macro

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