Searched refs:CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK (Results 1 - 10 of 10) sorted by relevance
| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/ |
| H A D | amdgpu_fiji_baco.c | 106 { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK, CG_CLKPIN_CNTL__BCLK_AS_XCLK__SHIFT, 0, 0x0 },
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| H A D | amdgpu_polaris_baco.c | 109 { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK, CG_CLKPIN_CNTL__BCLK_AS_XCLK__SHIFT, 0, 0x0 },
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| H A D | amdgpu_tonga_baco.c | 114 { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK, CG_CLKPIN_CNTL__BCLK_AS_XCLK__SHIFT, 0, 0x0 },
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| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| H A D | amdgpu_cik.c | 1771 data &= ~CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK;
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| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/smu/ |
| H A D | smu_7_0_0_sh_mask.h | 237 #define CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK 0x4 macro
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| H A D | smu_7_1_1_sh_mask.h | 227 #define CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK 0x4 macro
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| H A D | smu_7_1_3_sh_mask.h | 255 #define CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK 0x4 macro
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| H A D | smu_7_1_2_sh_mask.h | 229 #define CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK 0x4 macro
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| H A D | smu_7_1_0_sh_mask.h | 227 #define CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK 0x4 macro
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| H A D | smu_7_0_1_sh_mask.h | 229 #define CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK 0x4 macro
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