Searched refs:CG_CLKPIN_CNTL_DC__XTALIN_SEL_MASK (Results 1 - 6 of 6) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
H A Damdgpu_ci_baco.c95 { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_CLKPIN_CNTL_DC__XTALIN_SEL_MASK, CG_CLKPIN_CNTL_DC__XTALIN_SEL__SHIFT, 0, 0x0 },
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/smu/
H A Dsmu_7_1_1_sh_mask.h261 #define CG_CLKPIN_CNTL_DC__XTALIN_SEL_MASK 0x1c00 macro
H A Dsmu_7_1_3_sh_mask.h289 #define CG_CLKPIN_CNTL_DC__XTALIN_SEL_MASK 0x1c00 macro
H A Dsmu_7_1_2_sh_mask.h261 #define CG_CLKPIN_CNTL_DC__XTALIN_SEL_MASK 0x1c00 macro
H A Dsmu_7_1_0_sh_mask.h259 #define CG_CLKPIN_CNTL_DC__XTALIN_SEL_MASK 0x1c00 macro
H A Dsmu_7_0_1_sh_mask.h261 #define CG_CLKPIN_CNTL_DC__XTALIN_SEL_MASK 0x1c00 macro

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