Searched refs:BANK_WIDTH (Results 1 - 15 of 15) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_gfx_v6_0.c89 #define BANK_WIDTH(x) ((x) << 14) macro
428 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
436 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
444 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
451 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
463 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
471 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
479 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
491 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
499 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_
[all...]
H A Damdgpu_gfx_v8_0.c80 #define BANK_WIDTH(x) ((x) << GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT) macro
2220 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2224 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2228 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2232 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2236 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2240 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2244 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2248 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2252 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_
[all...]
H A Damdgpu_gfx_v7_0.c1166 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1170 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1174 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1178 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1182 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1186 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1190 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1194 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1198 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1202 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_
[all...]
H A Dcikd.h198 # define BANK_WIDTH(x) ((x) << 0) macro
H A Dsid.h1206 # define BANK_WIDTH(x) ((x) << 14) macro
H A Damdgpu_dce_v10_0.c1996 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
H A Damdgpu_dce_v11_0.c2038 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
H A Damdgpu_dce_v6_0.c1945 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
H A Damdgpu_dce_v8_0.c1917 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
/netbsd-current/sys/external/bsd/drm2/dist/drm/radeon/
H A Dradeon_si.c2532 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2541 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2550 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2559 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2568 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2577 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2586 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2595 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2604 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2613 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_
[all...]
H A Dradeon_cik.c2462 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2466 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2470 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2474 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2478 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2482 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2486 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2490 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2494 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2498 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_
[all...]
H A Dcikd.h1262 # define BANK_WIDTH(x) ((x) << 0) macro
H A Dsid.h1208 # define BANK_WIDTH(x) ((x) << 14) macro
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm.c3265 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/
H A Dnavi10_enum.h1743 * BANK_WIDTH enum
1746 typedef enum BANK_WIDTH { enum
1751 } BANK_WIDTH; typedef in typeref:enum:BANK_WIDTH

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