Searched refs:tx_conf_write (Results 1 - 18 of 18) sorted by relevance

/netbsd-6-1-5-RELEASE/sys/arch/hpcmips/tx/
H A Dtx39power.c112 tx_conf_write(tc, TX39_POWERCTRL_REG, reg);
121 tx_conf_write(tc, TX39_POWERCTRL_REG, reg);
170 tx_conf_write(tc, TX39_INTRENABLE6_REG, TX39_INTRENABLE6_GLOBALEN);
171 tx_conf_write(tc, TX39_INTRENABLE1_REG, 0);
172 tx_conf_write(tc, TX39_INTRENABLE2_REG, 0);
173 tx_conf_write(tc, TX39_INTRENABLE3_REG, 0);
174 tx_conf_write(tc, TX39_INTRENABLE4_REG, 0);
175 tx_conf_write(tc, TX39_INTRENABLE5_REG, 0);
177 tx_conf_write(tc, TX39_INTRENABLE7_REG, 0);
178 tx_conf_write(t
[all...]
H A Dtx39spi.c80 tx_conf_write(tc, TX39_SPICTRL_REG, reg);
81 tx_conf_write(tc, TX39_INTRCLEAR5_REG, TX39_INTRSTATUS5_SPIBUFAVAILINT);
82 tx_conf_write(tc, TX39_INTRCLEAR5_REG, TX39_INTRSTATUS5_SPIERRINT);
83 tx_conf_write(tc, TX39_INTRCLEAR5_REG, TX39_INTRSTATUS5_SPIRCVINT);
84 tx_conf_write(tc, TX39_INTRCLEAR5_REG, TX39_INTRSTATUS5_SPIEMPTYINT);
150 tx_conf_write(tc, TX39_INTRCLEAR5_REG, TX39_INTRSTATUS5_SPIBUFAVAILINT);
152 tx_conf_write(tc, TX39_SPITXHOLD_REG , w & 0xffff);
162 tx_conf_write(tc, TX39_INTRCLEAR5_REG, TX39_INTRSTATUS5_SPIRCVINT);
176 tx_conf_write(tc, TX39_SPICTRL_REG, reg);
184 tx_conf_write(t
[all...]
H A Dtx39icu.c254 tx_conf_write(tc, TX39_INTRENABLE1_REG, 0);
255 tx_conf_write(tc, TX39_INTRENABLE2_REG, 0);
256 tx_conf_write(tc, TX39_INTRENABLE3_REG, 0);
257 tx_conf_write(tc, TX39_INTRENABLE4_REG, 0);
258 tx_conf_write(tc, TX39_INTRENABLE5_REG, 0);
260 tx_conf_write(tc, TX39_INTRENABLE7_REG, 0);
261 tx_conf_write(tc, TX39_INTRENABLE8_REG, 0);
267 tx_conf_write(tc, TX39_INTRENABLE6_REG, reg);
271 tx_conf_write(tc, TX39_INTRCLEAR1_REG,
273 tx_conf_write(t
[all...]
H A Dtx39clock.c121 tx_conf_write(tc, TX39_TIMERCONTROL_REG, 0);
126 tx_conf_write(tc, TX39_TIMERCONTROL_REG, reg);
190 tx_conf_write(tc, TX39_TIMERCONTROL_REG, reg);
229 tx_conf_write(tc, TX39_TIMERCONTROL_REG, reg);
233 tx_conf_write(tc, TX39_TIMERCONTROL_REG, reg);
265 tx_conf_write(tc, TX39_TIMERPERIODIC_REG, reg);
272 tx_conf_write(tc, TX39_INTRENABLE6_REG, reg);
309 tx_conf_write(tc, TX39_TIMERALARMHI_REG, t.t_hi);
310 tx_conf_write(tc, TX39_TIMERALARMLO_REG, t.t_lo);
H A Dtx3912video.c157 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, val);
220 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, val);
228 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, val);
321 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg);
406 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg);
415 tx_conf_write(tc, TX3912_VIDEOCTRL3_REG, reg);
426 tx_conf_write(tc, TX3912_VIDEOCTRL4_REG, reg);
467 tx_conf_write(tc, TX3912_VIDEOCTRL2_REG, reg);
480 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg);
487 tx_conf_write(t
[all...]
H A Dtx39sib.c208 tx_conf_write(tc, TX39_SIBCTRL_REG, reg);
216 tx_conf_write(tc, TX39_SIBDMACTRL_REG, reg);
223 tx_conf_write(tc, TX39_SIBCTRL_REG, reg);
235 tx_conf_write(tc, TX39_SIBCTRL_REG, reg);
250 tx_conf_write(tc, TX39_SIBCTRL_REG, reg);
259 tx_conf_write(tc, TX39_SIBCTRL_REG, reg);
263 tx_conf_write(tc, TX39_SIBCTRL_REG, reg);
319 tx_conf_write(tc, TX39_INTRSTATUS1_REG, TX39_INTRSTATUS1_SIBSF0INT);
346 tx_conf_write(tc, TX39_SIBSF0CTRL_REG, reg);
364 tx_conf_write(t
[all...]
H A Dtxcom.c319 tx_conf_write(tc, TX39_CLOCKCTRL_REG, reg);
322 tx_conf_write(tc, ofs, 0);
349 tx_conf_write(tc, TX39_CLOCKCTRL_REG, reg);
356 tx_conf_write(tc, ofs, reg);
362 tx_conf_write(tc, ofs, reg);
394 tx_conf_write(tc, TX39_UARTCTRL1_REG(slot), reg);
399 tx_conf_write(tc, TX39_CLOCKCTRL_REG, reg);
434 tx_conf_write(tc, ofs, reg);
477 tx_conf_write(tc, TX39_UARTTXHOLD_REG(chip->sc_slot),
499 tx_conf_write(chi
[all...]
H A Dtxcsbus.c280 tx_conf_write(tc, TX39_MEMCONFIG0_REG, reg);
290 tx_conf_write(tc, TX39_MEMCONFIG1_REG, reg);
299 tx_conf_write(tc, TX39_MEMCONFIG0_REG, reg);
307 tx_conf_write(tc, TX39_MEMCONFIG1_REG, reg);
326 tx_conf_write(tc, TX39_MEMCONFIG3_REG, reg);
347 tx_conf_write(tc, TX39_MEMCONFIG3_REG, reg);
H A Dtx39ir.c103 tx_conf_write(tc, TX39_IRCTRL1_REG, reg);
108 tx_conf_write(tc, TX39_CLOCKCTRL_REG, reg);
H A Dtx39var.h97 #define tx_conf_write(t, reg, val) ( \ macro
H A Dtx39biu.c105 tx_conf_write(tc, TX39_MEMCONFIG4_REG, reg);
157 tx_conf_write(tc, TX39_MEMCONFIG4_REG, reg);
160 tx_conf_write(tc, TX39_MEMCONFIG4_REG, reg);
H A Dtx39io.c234 tx_conf_write(tc, TX39_IOMFIODATAOUT_REG, reg);
319 tx_conf_write(tc, TX39_IOCTRL_REG, reg);
399 tx_conf_write(tc, TX392X_IODATAINOUT_REG, reg);
/netbsd-6-1-5-RELEASE/sys/arch/hpcmips/dev/
H A Ducbsnd.c263 tx_conf_write(tc, TX39_SIBSF0CTRL_REG, reg);
274 tx_conf_write(tc, TX39_SIBSF0CTRL_REG, reg);
278 tx_conf_write(tc, TX39_SIBCTRL_REG,
288 tx_conf_write(tc, TX39_SIBSF0CTRL_REG, reg);
311 tx_conf_write(tc, TX39_SIBSF0CTRL_REG, reg);
351 tx_conf_write(tc, TX39_SIBSNDTXSTART_REG,
355 tx_conf_write(tc, TX39_SIBSIZE_REG,
358 tx_conf_write(tc, TX39_SIBSF0CTRL_REG, TX39_SIBSF0_SNDVALID);
363 tx_conf_write(tc, TX39_SIBDMACTRL_REG, reg);
391 tx_conf_write(t
[all...]
H A Dteliosio.c266 tx_conf_write(tc, TX392X_IODATAINOUT_REG, reg);
273 tx_conf_write(tc, TX392X_IODATAINOUT_REG, reg);
291 tx_conf_write(tc, TX392X_IODATAINOUT_REG, reg);
300 tx_conf_write(tc, TX392X_IODATAINOUT_REG, reg);
H A Doptpoint.c163 tx_conf_write(tc, TX39_INTRCLEAR4_REG,
188 tx_conf_write(tc, TX39_INTRCLEAR4_REG, TX39_INTRSTATUS4_OPTPOINTINT);
282 tx_conf_write(tc, TX39_INTRCLEAR4_REG, TX39_INTRSTATUS4_OPTPOINTINT);
H A Ducbtp.c574 tx_conf_write(tc, TX39_SIBSF0CTRL_REG, reg);
624 tx_conf_write(tc, TX39_SIBSF0CTRL_REG, reg);
H A Dit8368.c567 tx_conf_write(sc->sc_tc, TX39_MEMCONFIG3_REG, reg32);
/netbsd-6-1-5-RELEASE/sys/arch/hpcmips/stand/pbsdboot/
H A Dtx39xx.c57 tx_conf_write(tx_chipset_tag_t t, int reg, u_int32_t val) function

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