Searched refs:tx_conf_read (Results 1 - 18 of 18) sorted by relevance

/netbsd-6-1-5-RELEASE/sys/arch/hpcmips/tx/
H A Dtx39icu.c235 regs[0] = tx_conf_read(tc, TX39_INTRSTATUS6_REG);
236 regs[1] = tx_conf_read(tc, TX39_INTRSTATUS1_REG);
237 regs[2] = tx_conf_read(tc, TX39_INTRSTATUS2_REG);
238 regs[3] = tx_conf_read(tc, TX39_INTRSTATUS3_REG);
239 regs[4] = tx_conf_read(tc, TX39_INTRSTATUS4_REG);
240 regs[5] = tx_conf_read(tc, TX39_INTRSTATUS5_REG);
242 regs[7] = tx_conf_read(tc, TX39_INTRSTATUS7_REG);
243 regs[8] = tx_conf_read(tc, TX39_INTRSTATUS8_REG);
265 reg = tx_conf_read(tc, TX39_INTRENABLE6_REG);
272 tx_conf_read(t
[all...]
H A Dtx39power.c110 reg = tx_conf_read(tc, TX39_POWERCTRL_REG);
115 reg = tx_conf_read(tc, TX39_POWERCTRL_REG);
156 reg = tx_conf_read(tc, TX39_POWERCTRL_REG);
159 iregs[0] = tx_conf_read(tc, TX39_INTRENABLE6_REG);
160 iregs[1] = tx_conf_read(tc, TX39_INTRENABLE1_REG);
161 iregs[2] = tx_conf_read(tc, TX39_INTRENABLE2_REG);
162 iregs[3] = tx_conf_read(tc, TX39_INTRENABLE3_REG);
163 iregs[4] = tx_conf_read(tc, TX39_INTRENABLE4_REG);
164 iregs[5] = tx_conf_read(tc, TX39_INTRENABLE5_REG);
166 iregs[7] = tx_conf_read(t
[all...]
H A Dtx39spi.c78 reg = tx_conf_read(tc, TX39_SPICTRL_REG);
140 return tx_conf_read(sc->sc_tc, TX39_SPICTRL_REG) & (TX39_SPICTRL_EMPTY);
148 while(!(tx_conf_read(tc, TX39_INTRSTATUS5_REG) & TX39_INTRSTATUS5_SPIBUFAVAILINT))
160 while(!(tx_conf_read(tc, TX39_INTRSTATUS5_REG) & TX39_INTRSTATUS5_SPIRCVINT))
164 return tx_conf_read(tc, TX39_SPIRXHOLD_REG) & 0xffff;
171 txreg_t reg = tx_conf_read(tc, TX39_SPICTRL_REG);
183 txreg_t reg = tx_conf_read(tc, TX39_SPICTRL_REG);
191 txreg_t reg = tx_conf_read(tc, TX39_SPICTRL_REG);
199 txreg_t reg = tx_conf_read(tc, TX39_SPICTRL_REG);
211 txreg_t reg = tx_conf_read(t
[all...]
H A Dtx39clock.c124 reg = tx_conf_read(tc, TX39_TIMERCONTROL_REG);
181 reg = tx_conf_read(tc, TX39_TIMERCONTROL_REG);
205 oreglo = tx_conf_read(tc, TX39_TIMERRTCLO_REG);
206 reglo = tx_conf_read(tc, TX39_TIMERRTCLO_REG);
208 oreghi = tx_conf_read(tc, TX39_TIMERRTCHI_REG);
209 reghi = tx_conf_read(tc, TX39_TIMERRTCHI_REG);
225 reg = tx_conf_read(tc, TX39_TIMERCONTROL_REG);
247 return tx_conf_read(tc, TX39_TIMERRTCLO_REG);
262 reg = tx_conf_read(tc, TX39_TIMERPERIODIC_REG);
270 reg = tx_conf_read(t
[all...]
H A Dtx39io.c229 reg = tx_conf_read(tc, TX39_IOMFIODATAOUT_REG);
243 return (tx_conf_read(sc->sc_tc, TX39_IOMFIODATAIN_REG) & (1 << port));
271 stat_mfio->dir = tx_conf_read(tc, TX39_IOMFIODATADIR_REG);
272 stat_mfio->in = tx_conf_read(tc, TX39_IOMFIODATAIN_REG);
273 stat_mfio->out = tx_conf_read(tc, TX39_IOMFIODATAOUT_REG);
274 stat_mfio->power = tx_conf_read(tc, TX39_IOMFIOPOWERDWN_REG);
275 stat_mfio->u.select = tx_conf_read(tc, TX39_IOMFIODATASEL_REG);
286 txreg_t reg = tx_conf_read(sc->sc_tc, TX39_IOCTRL_REG);
311 reg = tx_conf_read(tc, TX39_IOCTRL_REG);
332 reg = tx_conf_read(t
[all...]
H A Dtx39biu.c102 reg = tx_conf_read(tc, TX39_MEMCONFIG4_REG);
107 reg = tx_conf_read(tc, TX39_MEMCONFIG4_REG);
155 reg = tx_conf_read(tc, TX39_MEMCONFIG4_REG);
158 reg = tx_conf_read(tc, TX39_MEMCONFIG4_REG);
181 reg = tx_conf_read(tc, TX39_MEMCONFIG0_REG);
231 reg = tx_conf_read(tc, TX39_MEMCONFIG3_REG);
259 reg = tx_conf_read(tc, TX39_MEMCONFIG4_REG);
H A Dtx39sib.c211 reg = tx_conf_read(tc, TX39_SIBDMACTRL_REG);
221 reg = tx_conf_read(tc, TX39_SIBCTRL_REG);
233 reg = tx_conf_read(tc, TX39_SIBCTRL_REG);
248 reg = tx_conf_read(tc, TX39_SIBCTRL_REG);
255 reg = tx_conf_read(tc, TX39_SIBCTRL_REG);
320 for (i = 0; (!(tx_conf_read(tc, TX39_INTRSTATUS1_REG) &
367 reg = tx_conf_read(tc, TX39_SIBSF0STAT_REG);
389 reg = tx_conf_read(tc, TX39_SIBCTRL_REG);
410 reg = tx_conf_read(tc, TX39_SIBDMACTRL_REG);
H A Dtx39ir.c101 reg = tx_conf_read(tc, TX39_IRCTRL1_REG);
106 reg = tx_conf_read(tc, TX39_CLOCKCTRL_REG);
134 reg = tx_conf_read(tc, TX39_IRCTRL1_REG);
H A Dtxcsbus.c278 reg = tx_conf_read(tc, TX39_MEMCONFIG0_REG);
286 reg = tx_conf_read(tc, TX39_MEMCONFIG1_REG);
297 reg = tx_conf_read(tc, TX39_MEMCONFIG0_REG);
303 reg = tx_conf_read(tc, TX39_MEMCONFIG1_REG);
311 reg = tx_conf_read(tc, TX39_MEMCONFIG3_REG);
332 reg = tx_conf_read(tc, TX39_MEMCONFIG3_REG);
H A Dtx39var.h95 #define tx_conf_read(t, reg) ( \ macro
H A Dtxcom.c317 reg = tx_conf_read(tc, TX39_CLOCKCTRL_REG);
347 reg = tx_conf_read(tc, TX39_CLOCKCTRL_REG);
354 reg = tx_conf_read(tc, ofs);
359 reg = tx_conf_read(tc, ofs);
366 while(!(tx_conf_read(tc, ofs) & TX39_UARTCTRL1_UARTON) &&
388 reg = tx_conf_read(tc, TX39_UARTCTRL1_REG(slot));
397 reg = tx_conf_read(tc, TX39_CLOCKCTRL_REG);
410 if (tx_conf_read(tc, ofs) & TX39_UARTCTRL1_EMPTY)
428 reg = tx_conf_read(tc, ofs);
451 while(!(TX39_UARTCTRL1_RXHOLDFULL & tx_conf_read(t
[all...]
H A Dtx3912video.c155 val = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG);
218 val = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG);
226 val = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG);
306 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG);
317 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG);
404 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG);
443 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG);
476 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG);
H A Dtx39.c135 rev = tx_conf_read(tc, TX3922_REVISION_REG);
/netbsd-6-1-5-RELEASE/sys/arch/hpcmips/dev/
H A Dteliosio.c231 reg = tx_conf_read(tc, TX392X_IODATAINOUT_REG);
260 reg = tx_conf_read(tc, TX392X_IODATAINOUT_REG);
271 reg = tx_conf_read(tc, TX392X_IODATAINOUT_REG);
289 reg = tx_conf_read(tc, TX392X_IODATAINOUT_REG);
296 reg = tx_conf_read(tc, TX392X_IODATAINOUT_REG);
H A Ducbsnd.c277 reg = tx_conf_read(tc, TX39_SIBCTRL_REG);
294 reg = tx_conf_read(tc, TX39_SIBSF0STAT_REG);
361 reg = tx_conf_read(tc, TX39_SIBDMACTRL_REG);
432 reg = tx_conf_read(tc, TX39_SIBSF0STAT_REG);
456 reg = tx_conf_read(tc, TX39_SIBCTRL_REG);
H A Dit8368.c552 reg32 = tx_conf_read(sc->sc_tc, TX39_MEMCONFIG3_REG);
574 reg32 = tx_conf_read(sc->sc_tc, TX39_MEMCONFIG3_REG);
H A Ducbtp.c579 reg = tx_conf_read(tc, TX39_SIBSF0STAT_REG);
/netbsd-6-1-5-RELEASE/sys/arch/hpcmips/stand/pbsdboot/
H A Dtx39xx.c51 tx_conf_read(tx_chipset_tag_t t, int reg) function

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