Searched refs:reg1 (Results 1 - 25 of 104) sorted by relevance

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/netbsd-6-1-5-RELEASE/external/gpl3/gcc/dist/gcc/testsuite/gcc.c-torture/execute/
H A D930930-1.c7 f (mr_TR, mr_SPB, mr_HB, reg1, reg2)
11 long *reg1;
18 if (reg1 < reg2)
20 if ((long *) *reg1 < mr_HB && (long *) *reg1 >= mr_SPB)
21 *--mr_TR = *reg1;
22 reg1--;
/netbsd-6-1-5-RELEASE/gnu/dist/gcc4/gcc/testsuite/gcc.c-torture/execute/
H A D930930-1.c7 f (mr_TR, mr_SPB, mr_HB, reg1, reg2)
11 long *reg1;
18 if (reg1 < reg2)
20 if ((long *) *reg1 < mr_HB && (long *) *reg1 >= mr_SPB)
21 *--mr_TR = *reg1;
22 reg1--;
/netbsd-6-1-5-RELEASE/sys/arch/powerpc/pci/
H A Dpchb.c80 pcireg_t reg1, reg2; local
83 reg1 = pci_conf_read(pa->pa_pc, pa->pa_tag, MPC105_PICR1);
103 switch (reg1 & MPC105_PICR1_L2_MP) {
123 pcireg_t reg1, reg2; local
126 reg1 = pci_conf_read(pa->pa_pc, pa->pa_tag, MPC106_PICR1);
146 switch (reg1 & MPC106_PICR1_EXT_L2_EN) {
148 switch (reg1 & MPC106_PICR1_L2_MP) {
164 switch (reg1 & MPC106_PICR1_L2_MP) {
182 pcireg_t reg1; local
188 reg1
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/netbsd-6-1-5-RELEASE/external/gpl3/gcc/dist/gcc/testsuite/gcc.target/i386/
H A Dpr22362.c7 register unsigned int reg1 __asm__ ("edi");
/netbsd-6-1-5-RELEASE/gnu/dist/gcc4/gcc/testsuite/gcc.target/i386/
H A Dpr22362.c7 register unsigned int reg1 __asm__ ("edi");
/netbsd-6-1-5-RELEASE/gnu/dist/gcc4/gcc/
H A Dconflict.c184 conflict_graph_add (conflict_graph graph, int reg1, int reg2)
186 int smaller = MIN (reg1, reg2);
187 int larger = MAX (reg1, reg2);
193 gcc_assert (reg1 != reg2);
228 conflict_graph_conflict_p (conflict_graph graph, int reg1, int reg2)
232 arc.smaller = MIN (reg1, reg2);
233 arc.larger = MAX (reg1, reg2);
309 print_conflict (int reg1, int reg2, void *contextp)
324 if (reg1 == context->reg)
329 reg = reg1;
183 conflict_graph_add(conflict_graph graph, int reg1, int reg2) argument
227 conflict_graph_conflict_p(conflict_graph graph, int reg1, int reg2) argument
308 print_conflict(int reg1, int reg2, void *contextp) argument
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/netbsd-6-1-5-RELEASE/sys/arch/sgimips/ioc/
H A Doioc.c101 uint32_t reg1, reg2; local
121 reg1 = 12 << OIOC2_CONFIG_HIWAT_SHFT;
122 reg1 |= OIOC2_CONFIG_BURST_MASK;
123 bus_space_write_4(sc->sc_iot, sc->sc_ioh, OIOC2_CONFIG, reg1);
126 if ((reg2 & (reg1 | OIOC2_CONFIG_NOSYNC_MASK)) == reg1)
/netbsd-6-1-5-RELEASE/sys/arch/hppa/spmath/
H A Dmd.h75 #define mdrr(reg1,reg2,result) {result_hi = reg1;result_lo = reg2;}
/netbsd-6-1-5-RELEASE/external/gpl3/binutils/dist/gas/config/
H A Dtc-microblaze.c796 unsigned reg1; local
841 op_end = parse_reg (op_end + 1, &reg1); /* Get rd. */
845 reg1 = 0;
863 if (check_spl_reg (& reg1))
873 inst |= (reg1 << RD_LOW) & RD_MASK;
879 inst |= (reg1 << RD_LOW) & RD_MASK;
888 op_end = parse_reg (op_end + 1, &reg1); /* Get rd. */
892 reg1 = 0;
907 if (check_spl_reg (& reg1))
959 count = 32 - reg1;
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/netbsd-6-1-5-RELEASE/external/gpl3/gcc/dist/gcc/
H A Dauto-inc-dec.c130 the forms are reg1 + reg2. */
266 for the reg1-reg2 case. Note that we do not have a INC_POS_REG
295 /* Parsed fields of an inc insn of the form "reg_res = reg0+reg1" or
302 bool reg1_is_const; /* True if reg1 is const, false if reg1 is a reg. */
306 rtx reg1; member in struct:inc_insn
307 enum inc_state reg1_state;/* The form of the const if reg1 is a const. */
308 HOST_WIDE_INT reg1_val;/* Value if reg1 is const. */
335 REGNO (inc_insn.reg0), REGNO (inc_insn.reg1));
347 REGNO (inc_insn.reg_res), REGNO (inc_insn.reg1));
366 rtx reg1; /* This is either a reg or a const depending on member in struct:mem_insn
1284 rtx reg1 = XEXP (XEXP (x, 0), 1); local
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H A Dira-conflicts.c342 process_regs_for_copy (rtx reg1, rtx reg2, bool constraint_p,
353 gcc_assert (REG_SUBREG_P (reg1) && REG_SUBREG_P (reg2));
354 only_regs_p = REG_P (reg1) && REG_P (reg2);
355 reg1 = go_through_subreg (reg1, &offset1);
359 if (HARD_REGISTER_P (reg1))
363 allocno_preferenced_hard_regno = REGNO (reg1) + offset1 - offset2;
369 a = ira_curr_regno_allocno_map[REGNO (reg1)];
371 else if (!CONFLICT_ALLOCNO_P (ira_curr_regno_allocno_map[REGNO (reg1)],
375 cp = ira_add_allocno_copy (ira_curr_regno_allocno_map[REGNO (reg1)],
340 process_regs_for_copy(rtx reg1, rtx reg2, bool constraint_p, rtx insn, int freq) argument
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/netbsd-6-1-5-RELEASE/sys/dev/ic/
H A Drtwvar.h118 * Complete outstanding read and/or write ops on [reg0, reg1]
119 * ([reg1, reg0]) before starting new ops on the same region. See
123 rtw_barrier(const struct rtw_regs *r, int reg0, int reg1, int flags) argument
125 bus_space_barrier(r->r_bt, r->r_bh, MIN(reg0, reg1),
126 MAX(reg0, reg1) - MIN(reg0, reg1) + 4, flags);
133 #define RTW_SYNC(regs, reg0, reg1) \
134 rtw_barrier(regs, reg0, reg1, BUS_SPACE_BARRIER_SYNC)
137 #define RTW_WBW(regs, reg0, reg1) \
138 rtw_barrier(regs, reg0, reg1, BUS_SPACE_BARRIER_WRITE_BEFORE_WRIT
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/netbsd-6-1-5-RELEASE/sys/arch/hpcsh/dev/
H A Dpsh3lcd.c72 uint8_t reg1; member in struct:psh3lcd_x0_bcd
83 uint8_t reg1; member in struct:psh3lcd_xx0_bcd
144 bcr1 == psh3lcd_x0_bcd[i].reg1 &&
161 for (i = 0; psh3lcd_xx0_bcd[i].reg1 != 0; i++)
162 if (bcr1 == psh3lcd_xx0_bcd[i].reg1 &&
165 if (psh3lcd_xx0_bcd[i].reg1 == 0)
174 _reg_write_1(PSH3LCD_BRIGHTNESS_REG1, psh3lcd_xx0_bcd[index].reg1);
183 _reg_write_1(PSH3LCD_BRIGHTNESS_REG1, psh3lcd_x0_bcd[index].reg1);
/netbsd-6-1-5-RELEASE/external/gpl3/binutils/dist/gas/
H A Ddw2gencfi.c113 unsigned reg1; member in struct:cfi_insn_data::__anon3257::__anon3259
284 cfi_add_CFA_insn_reg_reg (int insn, unsigned reg1, unsigned reg2)
289 insn_ptr->u.rr.reg1 = reg1;
345 cfi_add_CFA_register (unsigned reg1, unsigned reg2)
347 cfi_add_CFA_insn_reg_reg (DW_CFA_register, reg1, reg2);
538 unsigned reg1, reg2;
556 reg1 = cfi_parse_reg ();
559 cfi_add_CFA_offset (reg1, offset);
563 reg1
283 cfi_add_CFA_insn_reg_reg(int insn, unsigned reg1, unsigned reg2) argument
344 cfi_add_CFA_register(unsigned reg1, unsigned reg2) argument
536 unsigned reg1, reg2; local
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/netbsd-6-1-5-RELEASE/sys/arch/hp700/hp700/
H A Dlocore.S94 #define _DEBUG_PUTCHAR(reg1, reg2) ! \
95 ldil L%COM1_TX_REG, %reg1 ! \
96 stb %reg2, R%COM1_TX_REG(%sr1, %reg1) ! \
97 ldil L%10000000, %reg1 ! \
99 comb,<>,n %reg1, %r0, -8 ! \
100 sub %reg1, %reg2, %reg1
101 #define DEBUG_PUTCHAR(reg1, reg2, ch) ! \
103 _DEBUG_PUTCHAR(reg1,reg2)
104 #define _DEBUG_DUMPN(reg1, reg
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/netbsd-6-1-5-RELEASE/crypto/external/bsd/openssl/dist/crypto/perlasm/
H A Dx86gas.pl70 { my($addr,$reg1,$reg2,$idx)=@_;
77 $reg1 = "%$reg1" if ($reg1);
84 $ret .= "($reg1,$reg2,$idx)";
86 elsif ($reg1)
87 { $ret .= "($reg1)"; }
/netbsd-6-1-5-RELEASE/external/gpl3/gcc/dist/gcc/testsuite/gcc.c-torture/unsorted/
H A Dgen_tst.c16 #define reg1 r1 macro
31 char *a1[] = {"reg1", "indreg1", "imm1", "limm1",
H A DHIset.c12 #define reg1 r1 macro
27 {reg0 = reg1; }
59 {indreg0 = reg1; }
91 {adr0 = reg1; }
123 {adrreg0 = reg1; }
155 {adrx0 = reg1; }
187 {regx0 = reg1; }
H A DQIset.c12 #define reg1 r1 macro
27 {reg0 = reg1; }
59 {indreg0 = reg1; }
91 {adr0 = reg1; }
123 {adrreg0 = reg1; }
155 {adrx0 = reg1; }
187 {regx0 = reg1; }
H A DSFset.c12 #define reg1 r1 macro
27 {reg0 = reg1; }
59 {indreg0 = reg1; }
91 {adr0 = reg1; }
123 {adrreg0 = reg1; }
155 {adrx0 = reg1; }
187 {regx0 = reg1; }
H A DSIset.c12 #define reg1 r1 macro
27 {reg0 = reg1; }
59 {indreg0 = reg1; }
91 {adr0 = reg1; }
123 {adrreg0 = reg1; }
155 {adrx0 = reg1; }
187 {regx0 = reg1; }
/netbsd-6-1-5-RELEASE/gnu/dist/gcc4/gcc/testsuite/gcc.c-torture/unsorted/
H A Dgen_tst.c16 #define reg1 r1 macro
31 char *a1[] = {"reg1", "indreg1", "imm1", "limm1",
H A DHIset.c12 #define reg1 r1 macro
27 {reg0 = reg1; }
59 {indreg0 = reg1; }
91 {adr0 = reg1; }
123 {adrreg0 = reg1; }
155 {adrx0 = reg1; }
187 {regx0 = reg1; }
H A DQIset.c12 #define reg1 r1 macro
27 {reg0 = reg1; }
59 {indreg0 = reg1; }
91 {adr0 = reg1; }
123 {adrreg0 = reg1; }
155 {adrx0 = reg1; }
187 {regx0 = reg1; }
H A DSFset.c12 #define reg1 r1 macro
27 {reg0 = reg1; }
59 {indreg0 = reg1; }
91 {adr0 = reg1; }
123 {adrreg0 = reg1; }
155 {adrx0 = reg1; }
187 {regx0 = reg1; }

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