1/* $NetBSD: rtwvar.h,v 1.42 2010/02/24 22:37:58 dyoung Exp $ */ 2/*- 3 * Copyright (c) 2004, 2005 David Young. All rights reserved. 4 * 5 * Driver for the Realtek RTL8180 802.11 MAC/BBP by David Young. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY 17 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 19 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David 20 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 22 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 24 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 27 * OF SUCH DAMAGE. 28 */ 29 30#ifndef _DEV_IC_RTWVAR_H_ 31#define _DEV_IC_RTWVAR_H_ 32 33#include <sys/queue.h> 34#include <sys/callout.h> 35 36#ifdef RTW_DEBUG 37#define RTW_DEBUG_TUNE 0x0000001 38#define RTW_DEBUG_PKTFILT 0x0000002 39#define RTW_DEBUG_XMIT 0x0000004 40#define RTW_DEBUG_XMIT_DESC 0x0000008 41#define RTW_DEBUG_NODE 0x0000010 42#define RTW_DEBUG_PWR 0x0000020 43#define RTW_DEBUG_ATTACH 0x0000040 44#define RTW_DEBUG_REGDUMP 0x0000080 45#define RTW_DEBUG_ACCESS 0x0000100 46#define RTW_DEBUG_RESET 0x0000200 47#define RTW_DEBUG_INIT 0x0000400 48#define RTW_DEBUG_IOSTATE 0x0000800 49#define RTW_DEBUG_RECV 0x0001000 50#define RTW_DEBUG_RECV_DESC 0x0002000 51#define RTW_DEBUG_IO_KICK 0x0004000 52#define RTW_DEBUG_INTR 0x0008000 53#define RTW_DEBUG_PHY 0x0010000 54#define RTW_DEBUG_PHYIO 0x0020000 55#define RTW_DEBUG_PHYBITIO 0x0040000 56#define RTW_DEBUG_TIMEOUT 0x0080000 57#define RTW_DEBUG_BUGS 0x0100000 58#define RTW_DEBUG_BEACON 0x0200000 59#define RTW_DEBUG_LED 0x0400000 60#define RTW_DEBUG_KEY 0x0800000 61#define RTW_DEBUG_XMIT_RSRC 0x1000000 62#define RTW_DEBUG_OACTIVE 0x2000000 63#define RTW_DEBUG_MAX 0x3ffffff 64 65extern int rtw_debug; 66#define RTW_DPRINTF(__flags, __x) \ 67 if ((rtw_debug & (__flags)) != 0) printf __x 68#define DPRINTF(__sc, __flags, __x) \ 69 if (((__sc)->sc_if.if_flags & IFF_DEBUG) != 0) \ 70 RTW_DPRINTF(__flags, __x) 71#define RTW_PRINT_REGS(__regs, __dvname, __where) \ 72 rtw_print_regs((__regs), (__dvname), (__where)) 73#else /* RTW_DEBUG */ 74#define RTW_DPRINTF(__flags, __x) 75#define DPRINTF(__sc, __flags, __x) 76#define RTW_PRINT_REGS(__regs, __dvname, __where) 77#endif /* RTW_DEBUG */ 78 79enum rtw_locale { 80 RTW_LOCALE_USA = 0, 81 RTW_LOCALE_EUROPE, 82 RTW_LOCALE_JAPAN, 83 RTW_LOCALE_UNKNOWN 84}; 85 86enum rtw_rfchipid { 87 RTW_RFCHIPID_RESERVED = 0, 88 RTW_RFCHIPID_INTERSIL = 1, 89 RTW_RFCHIPID_RFMD = 2, 90 RTW_RFCHIPID_PHILIPS = 3, 91 RTW_RFCHIPID_MAXIM = 4, 92 RTW_RFCHIPID_GCT = 5 93}; 94/* sc_flags */ 95#define RTW_F_DIGPHY 0x00000002 /* digital PHY */ 96#define RTW_F_DFLANTB 0x00000004 /* B antenna is default */ 97#define RTW_F_ANTDIV 0x00000010 /* h/w antenna diversity */ 98#define RTW_F_9356SROM 0x00000020 /* 93c56 SROM */ 99#define RTW_F_DK_VALID 0x00000040 /* keys in DK0-DK3 are valid */ 100#define RTW_C_RXWEP_40 0x00000080 /* h/w decrypts 40-bit WEP */ 101#define RTW_C_RXWEP_104 0x00000100 /* h/w decrypts 104-bit WEP */ 102 /* all PHY flags */ 103#define RTW_F_ALLPHY (RTW_F_DIGPHY|RTW_F_DFLANTB|RTW_F_ANTDIV) 104enum rtw_access {RTW_ACCESS_NONE = 0, 105 RTW_ACCESS_CONFIG = 1, 106 RTW_ACCESS_ANAPARM = 2}; 107 108struct rtw_regs { 109 bus_space_tag_t r_bt; 110 bus_space_handle_t r_bh; 111 bus_size_t r_sz; 112 enum rtw_access r_access; 113}; 114 115/* 116 * Bus barrier 117 * 118 * Complete outstanding read and/or write ops on [reg0, reg1] 119 * ([reg1, reg0]) before starting new ops on the same region. See 120 * acceptable bus_space_barrier(9) for the flag definitions. 121 */ 122static inline void 123rtw_barrier(const struct rtw_regs *r, int reg0, int reg1, int flags) 124{ 125 bus_space_barrier(r->r_bt, r->r_bh, MIN(reg0, reg1), 126 MAX(reg0, reg1) - MIN(reg0, reg1) + 4, flags); 127} 128 129/* 130 * Barrier convenience macros. 131 */ 132/* sync */ 133#define RTW_SYNC(regs, reg0, reg1) \ 134 rtw_barrier(regs, reg0, reg1, BUS_SPACE_BARRIER_SYNC) 135 136/* write-before-write */ 137#define RTW_WBW(regs, reg0, reg1) \ 138 rtw_barrier(regs, reg0, reg1, BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE) 139 140/* write-before-read */ 141#define RTW_WBR(regs, reg0, reg1) \ 142 rtw_barrier(regs, reg0, reg1, BUS_SPACE_BARRIER_WRITE_BEFORE_READ) 143 144/* read-before-read */ 145#define RTW_RBR(regs, reg0, reg1) \ 146 rtw_barrier(regs, reg0, reg1, BUS_SPACE_BARRIER_READ_BEFORE_READ) 147 148/* read-before-write */ 149#define RTW_RBW(regs, reg0, reg1) \ 150 rtw_barrier(regs, reg0, reg1, BUS_SPACE_BARRIER_READ_BEFORE_WRITE) 151 152#define RTW_WBRW(regs, reg0, reg1) \ 153 rtw_barrier(regs, reg0, reg1, \ 154 BUS_SPACE_BARRIER_WRITE_BEFORE_READ | \ 155 BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE) 156 157#define RTW_SR_GET(sr, ofs) \ 158 (((sr)->sr_content[(ofs)/2] >> (((ofs) % 2 == 0) ? 0 : 8)) & 0xff) 159 160#define RTW_SR_GET16(sr, ofs) \ 161 (RTW_SR_GET((sr), (ofs)) | (RTW_SR_GET((sr), (ofs) + 1) << 8)) 162 163struct rtw_srom { 164 uint16_t *sr_content; 165 uint16_t sr_size; 166}; 167 168struct rtw_rxsoft { 169 struct mbuf *rs_mbuf; 170 bus_dmamap_t rs_dmamap; 171}; 172 173struct rtw_txsoft { 174 SIMPLEQ_ENTRY(rtw_txsoft) ts_q; 175 struct mbuf *ts_mbuf; 176 bus_dmamap_t ts_dmamap; 177 struct ieee80211_node *ts_ni; /* destination node */ 178 u_int ts_first; /* 1st hw descriptor */ 179 u_int ts_last; /* last hw descriptor */ 180 struct ieee80211_duration ts_d0; 181 struct ieee80211_duration ts_dn; 182}; 183 184#define RTW_NTXPRI 4 /* number of Tx priorities */ 185#define RTW_TXPRILO 0 186#define RTW_TXPRIMD 1 187#define RTW_TXPRIHI 2 188#define RTW_TXPRIBCN 3 /* beacon priority */ 189 190#define RTW_MAXPKTSEGS 64 /* Max 64 segments per Tx packet */ 191 192#define CASSERT(cond, complaint) complaint[(cond) ? 0 : -1] = complaint[(cond) ? 0 : -1] 193 194/* Note well: the descriptor rings must begin on RTW_DESC_ALIGNMENT 195 * boundaries. I allocate them consecutively from one buffer, so 196 * just round up. 197 */ 198#define RTW_TXQLENLO 64 /* low-priority queue length */ 199#define RTW_TXQLENMD 64 /* medium-priority */ 200#define RTW_TXQLENHI 64 /* high-priority */ 201#define RTW_TXQLENBCN 8 /* beacon */ 202 203#define RTW_NTXDESCLO RTW_TXQLENLO 204#define RTW_NTXDESCMD RTW_TXQLENMD 205#define RTW_NTXDESCHI RTW_TXQLENHI 206#define RTW_NTXDESCBCN RTW_TXQLENBCN 207 208#define RTW_NTXDESCTOTAL (RTW_NTXDESCLO + RTW_NTXDESCMD + \ 209 RTW_NTXDESCHI + RTW_NTXDESCBCN) 210 211#define RTW_RXQLEN 64 212 213struct rtw_rxdesc_blk { 214 u_int rdb_ndesc; 215 u_int rdb_next; 216 bus_dma_tag_t rdb_dmat; 217 bus_dmamap_t rdb_dmamap; 218 struct rtw_rxdesc *rdb_desc; 219}; 220 221struct rtw_txdesc_blk { 222 u_int tdb_ndesc; 223 u_int tdb_next; 224 u_int tdb_nfree; 225 bus_dma_tag_t tdb_dmat; 226 bus_dmamap_t tdb_dmamap; 227 bus_addr_t tdb_physbase; 228 bus_addr_t tdb_ofs; 229 bus_size_t tdb_basereg; 230 uint32_t tdb_base; 231 struct rtw_txdesc *tdb_desc; 232}; 233 234#define RTW_NEXT_IDX(__htc, __idx) (((__idx) + 1) % (__htc)->tdb_ndesc) 235 236#define RTW_NEXT_DESC(__htc, __idx) \ 237 ((__htc)->tdb_physbase + \ 238 sizeof(struct rtw_txdesc) * RTW_NEXT_IDX((__htc), (__idx))) 239 240SIMPLEQ_HEAD(rtw_txq, rtw_txsoft); 241 242struct rtw_txsoft_blk { 243 /* dirty/free s/w descriptors */ 244 struct rtw_txq tsb_dirtyq; 245 struct rtw_txq tsb_freeq; 246 u_int tsb_ndesc; 247 int tsb_tx_timer; 248 struct rtw_txsoft *tsb_desc; 249 uint8_t tsb_poll; 250}; 251 252struct rtw_descs { 253 struct rtw_txdesc hd_txlo[RTW_NTXDESCLO]; 254 struct rtw_txdesc hd_txmd[RTW_NTXDESCMD]; 255 struct rtw_txdesc hd_txhi[RTW_NTXDESCMD]; 256 struct rtw_rxdesc hd_rx[RTW_RXQLEN]; 257 struct rtw_txdesc hd_bcn[RTW_NTXDESCBCN]; 258}; 259#define RTW_DESC_OFFSET(ring, i) offsetof(struct rtw_descs, ring[i]) 260#define RTW_RING_OFFSET(ring) RTW_DESC_OFFSET(ring, 0) 261#define RTW_RING_BASE(sc, ring) ((sc)->sc_desc_physaddr + \ 262 RTW_RING_OFFSET(ring)) 263 264/* Radio capture format for RTL8180. */ 265 266#define RTW_RX_RADIOTAP_PRESENT \ 267 ((1 << IEEE80211_RADIOTAP_TSFT) | \ 268 (1 << IEEE80211_RADIOTAP_FLAGS) | \ 269 (1 << IEEE80211_RADIOTAP_RATE) | \ 270 (1 << IEEE80211_RADIOTAP_CHANNEL) | \ 271 (1 << IEEE80211_RADIOTAP_LOCK_QUALITY) | \ 272 (1 << IEEE80211_RADIOTAP_DB_ANTSIGNAL) | \ 273 0) 274 275#define RTW_PHILIPS_RX_RADIOTAP_PRESENT \ 276 ((1 << IEEE80211_RADIOTAP_TSFT) | \ 277 (1 << IEEE80211_RADIOTAP_FLAGS) | \ 278 (1 << IEEE80211_RADIOTAP_RATE) | \ 279 (1 << IEEE80211_RADIOTAP_CHANNEL) | \ 280 (1 << IEEE80211_RADIOTAP_DB_ANTSIGNAL) | \ 281 0) 282 283struct rtw_rx_radiotap_header { 284 struct ieee80211_radiotap_header rr_ihdr; 285 uint64_t rr_tsft; 286 uint8_t rr_flags; 287 uint8_t rr_rate; 288 uint16_t rr_chan_freq; 289 uint16_t rr_chan_flags; 290 union { 291 struct { 292 uint16_t o_barker_lock; 293 uint8_t o_antsignal; 294 } u_other; 295 struct { 296 uint8_t p_antsignal; 297 } u_philips; 298 } rr_u; 299} __packed; 300 301#define RTW_TX_RADIOTAP_PRESENT \ 302 ((1 << IEEE80211_RADIOTAP_RATE) | \ 303 (1 << IEEE80211_RADIOTAP_CHANNEL) | \ 304 0) 305 306struct rtw_tx_radiotap_header { 307 struct ieee80211_radiotap_header rt_ihdr; 308 uint8_t rt_rate; 309 uint8_t rt_pad; 310 uint16_t rt_chan_freq; 311 uint16_t rt_chan_flags; 312} __packed; 313 314enum rtw_attach_state {FINISHED, FINISH_DESCMAP_LOAD, FINISH_DESCMAP_CREATE, 315 FINISH_DESC_MAP, FINISH_DESC_ALLOC, FINISH_RXMAPS_CREATE, 316 FINISH_TXMAPS_CREATE, FINISH_RESET, FINISH_READ_SROM, FINISH_PARSE_SROM, 317 FINISH_RF_ATTACH, FINISH_ID_STA, FINISH_TXDESCBLK_SETUP, 318 FINISH_TXCTLBLK_SETUP, DETACHED}; 319 320struct rtw_mtbl { 321 int (*mt_newstate)(struct ieee80211com *, 322 enum ieee80211_state, int); 323 void (*mt_recv_mgmt)(struct ieee80211com *, 324 struct mbuf *, struct ieee80211_node *, 325 int, int, uint32_t); 326 struct ieee80211_node *(*mt_node_alloc)(struct ieee80211_node_table*); 327 void (*mt_node_free)(struct ieee80211_node *); 328}; 329 330enum rtw_pwrstate { RTW_OFF = 0, RTW_SLEEP, RTW_ON }; 331 332typedef void (*rtw_continuous_tx_cb_t)(void *arg, int); 333 334struct rtw_phy { 335 struct rtw_rf *p_rf; 336 struct rtw_regs *p_regs; 337}; 338 339struct rtw_bbpset { 340 u_int bb_antatten; 341 u_int bb_chestlim; 342 u_int bb_chsqlim; 343 u_int bb_ifagcdet; 344 u_int bb_ifagcini; 345 u_int bb_ifagclimit; 346 u_int bb_lnadet; 347 u_int bb_sys1; 348 u_int bb_sys2; 349 u_int bb_sys3; 350 u_int bb_trl; 351 u_int bb_txagc; 352}; 353 354struct rtw_rf { 355 void (*rf_destroy)(struct rtw_rf *); 356 /* args: frequency, txpower, power state */ 357 int (*rf_init)(struct rtw_rf *, u_int, uint8_t, 358 enum rtw_pwrstate); 359 /* arg: power state */ 360 int (*rf_pwrstate)(struct rtw_rf *, enum rtw_pwrstate); 361 /* arg: frequency */ 362 int (*rf_tune)(struct rtw_rf *, u_int); 363 /* arg: txpower */ 364 int (*rf_txpower)(struct rtw_rf *, uint8_t); 365 rtw_continuous_tx_cb_t rf_continuous_tx_cb; 366 void *rf_continuous_tx_arg; 367 struct rtw_bbpset rf_bbpset; 368}; 369 370static __inline void 371rtw_rf_destroy(struct rtw_rf *rf) 372{ 373 (*rf->rf_destroy)(rf); 374} 375 376static __inline int 377rtw_rf_init(struct rtw_rf *rf, u_int freq, uint8_t opaque_txpower, 378 enum rtw_pwrstate power) 379{ 380 return (*rf->rf_init)(rf, freq, opaque_txpower, power); 381} 382 383static __inline int 384rtw_rf_pwrstate(struct rtw_rf *rf, enum rtw_pwrstate power) 385{ 386 return (*rf->rf_pwrstate)(rf, power); 387} 388 389static __inline int 390rtw_rf_tune(struct rtw_rf *rf, u_int freq) 391{ 392 return (*rf->rf_tune)(rf, freq); 393} 394 395static __inline int 396rtw_rf_txpower(struct rtw_rf *rf, uint8_t opaque_txpower) 397{ 398 return (*rf->rf_txpower)(rf, opaque_txpower); 399} 400 401typedef int (*rtw_rf_write_t)(struct rtw_regs *, enum rtw_rfchipid, u_int, 402 uint32_t); 403 404struct rtw_rfbus { 405 struct rtw_regs *b_regs; 406 rtw_rf_write_t b_write; 407}; 408 409static __inline int 410rtw_rfbus_write(struct rtw_rfbus *bus, enum rtw_rfchipid rfchipid, u_int addr, 411 uint32_t val) 412{ 413 return (*bus->b_write)(bus->b_regs, rfchipid, addr, val); 414} 415 416struct rtw_max2820 { 417 struct rtw_rf mx_rf; 418 struct rtw_rfbus mx_bus; 419 int mx_is_a; /* 1: MAX2820A/MAX2821A */ 420}; 421 422struct rtw_grf5101 { 423 struct rtw_rf gr_rf; 424 struct rtw_rfbus gr_bus; 425}; 426 427struct rtw_sa2400 { 428 struct rtw_rf sa_rf; 429 struct rtw_rfbus sa_bus; 430 int sa_digphy; /* 1: digital PHY */ 431}; 432 433typedef void (*rtw_pwrstate_t)(struct rtw_regs *, enum rtw_pwrstate, int, int); 434 435union rtw_keys { 436 uint8_t rk_keys[4][16]; 437 uint32_t rk_words[16]; 438}; 439 440#define RTW_LED_SLOW_TICKS MAX(1, hz/2) 441#define RTW_LED_FAST_TICKS MAX(1, hz/10) 442 443struct rtw_led_state { 444#define RTW_LED0 0x1 445#define RTW_LED1 0x2 446 uint8_t ls_slowblink:2; 447 uint8_t ls_actblink:2; 448 uint8_t ls_default:2; 449 uint8_t ls_state; 450 uint8_t ls_event; 451#define RTW_LED_S_RX 0x1 452#define RTW_LED_S_TX 0x2 453#define RTW_LED_S_SLOW 0x4 454 struct callout ls_slow_ch; 455 struct callout ls_fast_ch; 456}; 457 458struct rtw_softc { 459 device_t sc_dev; 460 device_suspensor_t sc_suspensor; 461 pmf_qual_t sc_qual; 462 463 struct ethercom sc_ec; 464 struct ieee80211com sc_ic; 465 struct rtw_regs sc_regs; 466 bus_dma_tag_t sc_dmat; 467 uint32_t sc_flags; 468 469 enum rtw_attach_state sc_attach_state; 470 enum rtw_rfchipid sc_rfchipid; 471 enum rtw_locale sc_locale; 472 uint8_t sc_phydelay; 473 474 /* s/w Tx/Rx descriptors */ 475 struct rtw_txsoft_blk sc_txsoft_blk[RTW_NTXPRI]; 476 struct rtw_txdesc_blk sc_txdesc_blk[RTW_NTXPRI]; 477 478 struct rtw_rxsoft sc_rxsoft[RTW_RXQLEN]; 479 struct rtw_rxdesc_blk sc_rxdesc_blk; 480 481 struct rtw_descs *sc_descs; 482 483 bus_dma_segment_t sc_desc_segs; 484 int sc_desc_nsegs; 485 bus_dmamap_t sc_desc_dmamap; 486#define sc_desc_physaddr sc_desc_dmamap->dm_segs[0].ds_addr 487 488 struct rtw_srom sc_srom; 489 490 enum rtw_pwrstate sc_pwrstate; 491 492 rtw_pwrstate_t sc_pwrstate_cb; 493 494 struct rtw_rf *sc_rf; 495 496 uint16_t sc_inten; 497 498 /* interrupt acknowledge hook */ 499 void (*sc_intr_ack)(struct rtw_regs *); 500 501 struct rtw_mtbl sc_mtbl; 502 503 struct bpf_if * sc_radiobpf; 504 505 struct callout sc_scan_ch; 506 u_int sc_cur_chan; 507 508 uint32_t sc_tsfth; /* most significant TSFT bits */ 509 uint32_t sc_rcr; /* RTW_RCR */ 510 uint8_t sc_csthr; /* carrier-sense threshold */ 511 512 int sc_do_tick; /* indicate 1s ticks */ 513 struct timeval sc_tick0; /* first tick */ 514 515 uint8_t sc_rev; /* PCI/Cardbus revision */ 516 517 uint32_t sc_anaparm; /* register RTW_ANAPARM */ 518 519 union { 520 struct rtw_rx_radiotap_header tap; 521 uint8_t pad[64]; 522 } sc_rxtapu; 523 union { 524 struct rtw_tx_radiotap_header tap; 525 uint8_t pad[64]; 526 } sc_txtapu; 527 union rtw_keys sc_keys; 528 struct ifqueue sc_beaconq; 529 struct rtw_led_state sc_led_state; 530 int sc_hwverid; 531}; 532 533#define sc_if sc_ec.ec_if 534#define sc_rxtap sc_rxtapu.tap 535#define sc_txtap sc_txtapu.tap 536 537void rtw_txdac_enable(struct rtw_softc *, int); 538void rtw_anaparm_enable(struct rtw_regs *, int); 539void rtw_config0123_enable(struct rtw_regs *, int); 540void rtw_continuous_tx_enable(struct rtw_softc *, int); 541void rtw_set_access(struct rtw_regs *, enum rtw_access); 542 543void rtw_attach(struct rtw_softc *); 544int rtw_detach(struct rtw_softc *); 545int rtw_intr(void *); 546 547bool rtw_suspend(device_t, const pmf_qual_t *); 548bool rtw_resume(device_t, const pmf_qual_t *); 549 550int rtw_activate(device_t, enum devact); 551 552const char *rtw_pwrstate_string(enum rtw_pwrstate); 553 554#endif /* _DEV_IC_RTWVAR_H_ */ 555