Searched refs:gpuobj (Results 1 - 16 of 16) sorted by relevance

/netbsd-6-1-5-RELEASE/sys/external/bsd/drm/dist/shared-core/
H A Dnouveau_object.c106 struct nouveau_gpuobj *ramht = chan->ramht ? chan->ramht->gpuobj : NULL;
107 struct nouveau_gpuobj *gpuobj = ref->gpuobj; local
118 (gpuobj->engine << NV_RAMHT_CONTEXT_ENGINE_SHIFT);
123 (gpuobj->engine << NV40_RAMHT_CONTEXT_ENGINE_SHIFT);
126 (gpuobj->engine << NV40_RAMHT_CONTEXT_ENGINE_SHIFT);
157 struct nouveau_gpuobj *ramht = chan->ramht ? chan->ramht->gpuobj : NULL;
195 struct nouveau_gpuobj *gpuobj; local
205 gpuobj = drm_calloc(1, sizeof(*gpuobj), DRM_MEM_DRIVE
315 struct nouveau_gpuobj *gpuobj = NULL; local
335 struct nouveau_gpuobj *gpuobj; local
375 nouveau_gpuobj_instance_get(struct drm_device *dev, struct nouveau_channel *chan, struct nouveau_gpuobj *gpuobj, uint32_t *inst) argument
422 nouveau_gpuobj_ref_add(struct drm_device *dev, struct nouveau_channel *chan, uint32_t handle, struct nouveau_gpuobj *gpuobj, struct nouveau_gpuobj_ref **ref_ret) argument
501 struct nouveau_gpuobj *gpuobj = NULL; local
542 struct nouveau_gpuobj *gpuobj = NULL; local
638 nouveau_gpuobj_dma_new(struct nouveau_channel *chan, int class, uint64_t offset, uint64_t size, int access, int target, struct nouveau_gpuobj **gpuobj) argument
778 nouveau_gpuobj_gart_dma_new(struct nouveau_channel *chan, uint64_t offset, uint64_t size, int access, struct nouveau_gpuobj **gpuobj, uint32_t *o_ret) argument
865 nouveau_gpuobj_gr_new(struct nouveau_channel *chan, int class, struct nouveau_gpuobj **gpuobj) argument
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H A Dnv04_instmem.c121 nv04_instmem_populate(struct drm_device *dev, struct nouveau_gpuobj *gpuobj, uint32_t *sz) argument
123 if (gpuobj->im_backing)
130 nv04_instmem_clear(struct drm_device *dev, struct nouveau_gpuobj *gpuobj) argument
134 if (gpuobj && gpuobj->im_backing) {
135 if (gpuobj->im_bound)
136 dev_priv->Engine.instmem.unbind(dev, gpuobj);
137 gpuobj->im_backing = NULL;
142 nv04_instmem_bind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj) argument
144 if (!gpuobj
152 nv04_instmem_unbind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj) argument
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H A Dnv50_instmem.c50 offset = chan->ramin->gpuobj->im_backing->start; \
97 * The main reason for creating a channel is so we can use the gpuobj
128 BAR0_WI32(chan->ramin->gpuobj, i, 0);
148 BAR0_WI32(priv->pramin_pt->gpuobj, i + 0, v | 1);
150 BAR0_WI32(priv->pramin_pt->gpuobj, i + 0, 0x00000009);
151 BAR0_WI32(priv->pramin_pt->gpuobj, i + 4, 0x00000000);
161 BAR0_WI32(priv->pramin_bar->gpuobj, 0x00, 0x7fc00000);
162 BAR0_WI32(priv->pramin_bar->gpuobj, 0x04, dev_priv->ramin->size - 1);
163 BAR0_WI32(priv->pramin_bar->gpuobj, 0x08, 0x00000000);
164 BAR0_WI32(priv->pramin_bar->gpuobj,
236 nv50_instmem_populate(struct drm_device *dev, struct nouveau_gpuobj *gpuobj, uint32_t *sz) argument
258 nv50_instmem_clear(struct drm_device *dev, struct nouveau_gpuobj *gpuobj) argument
271 nv50_instmem_bind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj) argument
312 nv50_instmem_unbind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj) argument
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H A Dnouveau_notifier.c71 struct nouveau_gpuobj *gpuobj)
75 if (gpuobj->priv)
76 nouveau_mem_free_block(gpuobj->priv);
70 nouveau_notifier_gpuobj_dtor(struct drm_device *dev, struct nouveau_gpuobj *gpuobj) argument
H A Dnv50_fifo.c54 INSTANCE_WR(cur->gpuobj, nr++, i);
238 uint32_t ramfc_offset = chan->ramin->gpuobj->im_pramin->start;
239 uint32_t vram_offset = chan->ramin->gpuobj->im_backing->start;
253 ramfc = chan->ramfc->gpuobj;
271 INSTANCE_WR(chan->ramin->gpuobj, 0, chan->id);
272 INSTANCE_WR(chan->ramin->gpuobj, 1, chan->ramfc->instance >> 8);
313 struct nouveau_gpuobj *ramfc = chan->ramfc->gpuobj;
H A Dnouveau_dma.c37 struct nouveau_gpuobj *gpuobj = NULL; local
90 if ((ret = nouveau_gpuobj_gr_new(dchan->chan, grclass, &gpuobj))) {
96 gpuobj, NULL))) {
H A Dnv04_fifo.c31 #define RAMFC_WR(offset,val) INSTANCE_WR(chan->ramfc->gpuobj, \
33 #define RAMFC_RD(offset) INSTANCE_RD(chan->ramfc->gpuobj, \
H A Dnv10_fifo.c32 #define RAMFC_WR(offset,val) INSTANCE_WR(chan->ramfc->gpuobj, \
34 #define RAMFC_RD(offset) INSTANCE_RD(chan->ramfc->gpuobj, \
H A Dnv50_graph.c169 struct nouveau_gpuobj *ramin = chan->ramin->gpuobj;
183 ctx = chan->ramin_grctx->gpuobj;
269 INSTANCE_WR(chan->ramin->gpuobj, i/4, 0);
H A Dnv40_fifo.c32 #define RAMFC_WR(offset,val) INSTANCE_WR(chan->ramfc->gpuobj, \
34 #define RAMFC_RD(offset) INSTANCE_RD(chan->ramfc->gpuobj, \
H A Dnv20_graph.c609 ctx_init(dev, chan->ramin_grctx->gpuobj);
611 /* nv20: INSTANCE_WR(chan->ramin_grctx->gpuobj, 10, chan->id<<24); */
612 INSTANCE_WR(chan->ramin_grctx->gpuobj, idoffs, (chan->id<<24)|0x1);
615 INSTANCE_WR(dev_priv->ctx_table->gpuobj, chan->id,
629 INSTANCE_WR(dev_priv->ctx_table->gpuobj, chan->id, 0);
H A Dnouveau_irq.c218 if (inst == INSTANCE_RD(chan->ramin_grctx->gpuobj, 0))
H A Dnouveau_drv.h90 struct nouveau_gpuobj *gpuobj; member in struct:nouveau_gpuobj_ref
H A Dnouveau_fifo.c407 struct nouveau_gpuobj *ramfc = chan->ramfc->gpuobj;
H A Dnv40_graph.c1517 ctx_init(dev, chan->ramin_grctx->gpuobj);
/netbsd-6-1-5-RELEASE/sys/external/bsd/drm/dist/bsd-core/
H A Dnouveau_sgdma.c99 struct nouveau_gpuobj *gpuobj = dev_priv->gart_info.sg_ctxdma;
123 INSTANCE_WR(gpuobj, i, pteval | 3);
125 INSTANCE_WR(gpuobj, (i<<1)+0, pteval | 0x21);
126 INSTANCE_WR(gpuobj, (i<<1)+1, 0x00000000);
143 struct nouveau_gpuobj *gpuobj = dev_priv->gart_info.sg_ctxdma;
151 INSTANCE_WR(gpuobj, pte, pteval | 3);
153 INSTANCE_WR(gpuobj, (pte<<1)+0, pteval | 0x21);
154 INSTANCE_WR(gpuobj, (pte<<1)+1, 0x00000000);
214 struct nouveau_gpuobj *gpuobj = NULL; local
231 NVOBJ_FLAG_ZERO_FREE, &gpuobj))) {
346 struct nouveau_gpuobj *gpuobj = dev_priv->gart_info.sg_ctxdma; local
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