Lines Matching refs:gpuobj
106 struct nouveau_gpuobj *ramht = chan->ramht ? chan->ramht->gpuobj : NULL;
107 struct nouveau_gpuobj *gpuobj = ref->gpuobj;
118 (gpuobj->engine << NV_RAMHT_CONTEXT_ENGINE_SHIFT);
123 (gpuobj->engine << NV40_RAMHT_CONTEXT_ENGINE_SHIFT);
126 (gpuobj->engine << NV40_RAMHT_CONTEXT_ENGINE_SHIFT);
157 struct nouveau_gpuobj *ramht = chan->ramht ? chan->ramht->gpuobj : NULL;
195 struct nouveau_gpuobj *gpuobj;
205 gpuobj = drm_calloc(1, sizeof(*gpuobj), DRM_MEM_DRIVER);
206 if (!gpuobj)
208 DRM_DEBUG("gpuobj %p\n", gpuobj);
209 gpuobj->flags = flags;
210 gpuobj->im_channel = chan ? chan->id : -1;
212 list_add_tail(&gpuobj->list, &dev_priv->gpuobj_list);
238 if (!chan && (ret = engine->instmem.populate(dev, gpuobj, &size))) {
239 nouveau_gpuobj_del(dev, &gpuobj);
244 gpuobj->im_pramin = nouveau_mem_alloc_block(pramin, size,
247 if (!gpuobj->im_pramin) {
248 nouveau_gpuobj_del(dev, &gpuobj);
251 gpuobj->im_pramin->flags = NOUVEAU_MEM_INSTANCE;
253 if (!chan && (ret = engine->instmem.bind(dev, gpuobj))) {
254 nouveau_gpuobj_del(dev, &gpuobj);
258 if (gpuobj->flags & NVOBJ_FLAG_ZERO_ALLOC) {
261 for (i = 0; i < gpuobj->im_pramin->size; i += 4)
262 INSTANCE_WR(gpuobj, i/4, 0);
265 *gpuobj_ret = gpuobj;
315 struct nouveau_gpuobj *gpuobj = NULL;
321 gpuobj = list_entry(entry, struct nouveau_gpuobj, list);
323 DRM_ERROR("gpuobj %p still exists at takedown, refs=%d\n",
324 gpuobj, gpuobj->refcount);
325 gpuobj->refcount = 0;
326 nouveau_gpuobj_del(dev, &gpuobj);
335 struct nouveau_gpuobj *gpuobj;
337 DRM_DEBUG("gpuobj %p\n", pgpuobj ? *pgpuobj : NULL);
341 gpuobj = *pgpuobj;
343 if (gpuobj->refcount != 0) {
344 DRM_ERROR("gpuobj refcount is %d\n", gpuobj->refcount);
348 if (gpuobj->dtor)
349 gpuobj->dtor(dev, gpuobj);
351 if (gpuobj->im_backing) {
352 if (gpuobj->flags & NVOBJ_FLAG_FAKE)
353 drm_free(gpuobj->im_backing,
354 sizeof(*gpuobj->im_backing), DRM_MEM_DRIVER);
356 engine->instmem.clear(dev, gpuobj);
359 if (gpuobj->im_pramin) {
360 if (gpuobj->flags & NVOBJ_FLAG_FAKE)
361 drm_free(gpuobj->im_pramin, sizeof(*gpuobj->im_pramin),
364 nouveau_mem_free_block(gpuobj->im_pramin);
367 list_del(&gpuobj->list);
370 drm_free(gpuobj, sizeof(*gpuobj), DRM_MEM_DRIVER);
377 struct nouveau_gpuobj *gpuobj, uint32_t *inst)
384 *inst = gpuobj->im_pramin->start;
388 if (chan && gpuobj->im_channel != chan->id) {
390 gpuobj->im_channel, chan->id);
396 cpramin = chan->ramin->gpuobj;
397 *inst = gpuobj->im_pramin->start - cpramin->im_pramin->start;
402 if (gpuobj->im_channel < 0) {
404 if (!gpuobj->im_backing) {
405 DRM_ERROR("AII, no VRAM backing gpuobj\n");
408 *inst = gpuobj->im_backing->start;
412 cpramin = dev_priv->fifos[gpuobj->im_channel]->ramin->gpuobj;
414 (gpuobj->im_pramin->start - cpramin->im_pramin->start);
423 uint32_t handle, struct nouveau_gpuobj *gpuobj,
431 DRM_DEBUG("ch%d h=0x%08x gpuobj=%p\n",
432 chan ? chan->id : -1, handle, gpuobj);
434 if (!dev_priv || !gpuobj || (ref_ret && *ref_ret != NULL))
440 ret = nouveau_gpuobj_instance_get(dev, chan, gpuobj, &instance);
447 ref->gpuobj = gpuobj;
464 ref->gpuobj->refcount++;
481 if (ref->gpuobj) {
482 ref->gpuobj->refcount--;
484 if (ref->gpuobj->refcount == 0) {
485 if (!(ref->gpuobj->flags & NVOBJ_FLAG_ALLOW_NO_REFS))
486 nouveau_gpuobj_del(dev, &ref->gpuobj);
501 struct nouveau_gpuobj *gpuobj = NULL;
504 if ((ret = nouveau_gpuobj_new(dev, oc, size, align, flags, &gpuobj)))
507 if ((ret = nouveau_gpuobj_ref_add(dev, rc, handle, gpuobj, ref))) {
508 nouveau_gpuobj_del(dev, &gpuobj);
542 struct nouveau_gpuobj *gpuobj = NULL;
548 gpuobj = drm_calloc(1, sizeof(*gpuobj), DRM_MEM_DRIVER);
549 if (!gpuobj)
551 DRM_DEBUG("gpuobj %p\n", gpuobj);
552 gpuobj->im_channel = -1;
553 gpuobj->flags = flags | NVOBJ_FLAG_FAKE;
555 list_add_tail(&gpuobj->list, &dev_priv->gpuobj_list);
558 gpuobj->im_pramin = drm_calloc(1, sizeof(struct mem_block),
560 if (!gpuobj->im_pramin) {
561 nouveau_gpuobj_del(dev, &gpuobj);
564 gpuobj->im_pramin->start = p_offset;
565 gpuobj->im_pramin->size = size;
569 gpuobj->im_backing = drm_calloc(1, sizeof(struct mem_block),
571 if (!gpuobj->im_backing) {
572 nouveau_gpuobj_del(dev, &gpuobj);
575 gpuobj->im_backing->start = b_offset;
576 gpuobj->im_backing->size = size;
579 if (gpuobj->flags & NVOBJ_FLAG_ZERO_ALLOC) {
580 for (i = 0; i < gpuobj->im_pramin->size; i += 4)
581 INSTANCE_WR(gpuobj, i/4, 0);
585 if ((i = nouveau_gpuobj_ref_add(dev, NULL, 0, gpuobj, pref))) {
586 nouveau_gpuobj_del(dev, &gpuobj);
592 *pgpuobj = gpuobj;
640 int target, struct nouveau_gpuobj **gpuobj)
674 gpuobj);
676 DRM_ERROR("Error creating gpuobj: %d\n", ret);
690 INSTANCE_WR(*gpuobj, 0, ((1<<12) | (1<<13) |
695 INSTANCE_WR(*gpuobj, 1, size - 1);
696 INSTANCE_WR(*gpuobj, 2, frame | pte_flags);
697 INSTANCE_WR(*gpuobj, 3, frame | pte_flags);
716 INSTANCE_WR(*gpuobj, 0, ((1<<12) | (0<<13) |
721 INSTANCE_WR(*gpuobj, 1, (uint32_t) size-1);
748 INSTANCE_WR(*gpuobj, instance_offset,
766 INSTANCE_WR(*gpuobj, 0, flags0 | class);
767 INSTANCE_WR(*gpuobj, 1, offset + size - 1);
768 INSTANCE_WR(*gpuobj, 2, offset);
769 INSTANCE_WR(*gpuobj, 5, flags5);
772 (*gpuobj)->engine = NVOBJ_ENGINE_SW;
773 (*gpuobj)->class = class;
780 struct nouveau_gpuobj **gpuobj,
792 NV_DMA_TARGET_AGP, gpuobj);
797 *gpuobj = dev_priv->gart_info.sg_ctxdma;
804 ret = (*gpuobj != NULL) ? 0 : -EINVAL;
866 struct nouveau_gpuobj **gpuobj)
878 gpuobj);
880 DRM_ERROR("Error creating gpuobj: %d\n", ret);
885 INSTANCE_WR(*gpuobj, 0, class);
886 INSTANCE_WR(*gpuobj, 5, 0x00010000);
890 INSTANCE_WR(*gpuobj, 0, 0x00001030);
891 INSTANCE_WR(*gpuobj, 1, 0xFFFFFFFF);
895 INSTANCE_WR(*gpuobj, 0, class);
897 INSTANCE_WR(*gpuobj, 2, 0x01000000);
901 INSTANCE_WR(*gpuobj, 0, class | 0x00080000);
903 INSTANCE_WR(*gpuobj, 0, class);
909 (*gpuobj)->engine = NVOBJ_ENGINE_GR;
910 (*gpuobj)->class = class;
951 pramin = chan->ramin->gpuobj;
995 vm_offset += chan->ramin->gpuobj->im_pramin->start;