Searched refs:csr (Results 1 - 25 of 181) sorted by relevance

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/netbsd-6-1-5-RELEASE/sys/arch/ews4800mips/stand/common/
H A Dcons_zs.c50 zs_set_addr(uint32_t csr, uint32_t data, int clock) argument
53 zs.csr = (volatile uint8_t *)csr;
65 *zs.csr = reg; \
66 *zs.csr = val; \
92 *zs.csr = ZSWR0_RESET_STATUS;
93 *zs.csr = ZSWR0_RESET_STATUS;
103 int csr, data; local
106 csr = *zs.csr;
117 int csr, data; local
131 int csr; local
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/netbsd-6-1-5-RELEASE/sys/dev/ic/
H A Dlsi64854.c88 uint32_t csr; local
114 csr = L64854_GCSR(sc);
115 sc->sc_rev = csr & L64854_DEVID;
140 DPRINTF(LDB_ANY, (", burst 0x%x, csr 0x%x", sc->sc_burst, csr));
207 uint32_t csr; local
210 csr = L64854_GCSR(sc);
212 DPRINTF(LDB_ANY, ("%s: csr 0x%x\n", __func__, csr));
221 L64854_SCSR(sc, csr | D_HW_RESET_FAS36
287 uint32_t csr; local
378 uint32_t csr; local
506 uint32_t csr; local
545 uint32_t csr; local
615 uint32_t csr; local
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H A Dmk48txx.c111 uint8_t csr; local
119 csr = (*sc->sc_nvrd)(sc, clkoff + MK48TXX_ICSR);
120 csr |= MK48TXX_CSR_READ;
121 (*sc->sc_nvwr)(sc, clkoff + MK48TXX_ICSR, csr);
132 year += 100*FROMBCD(csr & MK48TXX_CSR_CENT_MASK);
143 csr = (*sc->sc_nvrd)(sc, clkoff + MK48TXX_ICSR);
144 csr &= ~MK48TXX_CSR_READ;
145 (*sc->sc_nvwr)(sc, clkoff + MK48TXX_ICSR, csr);
160 uint8_t csr; local
180 csr
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H A Dwd33c93.c293 u_char csr, reg; local
320 GET_SBIC_csr(sc, csr); /* clears interrupt also */
323 switch (csr) {
882 int csr; local
883 GET_SBIC_csr(sc, csr);
884 printf("wd33c93_wait: TIMEO @%d with asr=x%x csr=x%x\n",
885 line, val, csr);
902 u_char csr, asr; local
905 GET_SBIC_csr(sc, csr);
908 printf ("ABORT in %s: csr
985 u_char target, lun, asr, csr, id; local
1270 u_char phase, csr; local
1312 u_char csr, asr; local
1379 u_char asr, csr; local
1423 u_char asr, csr=0; local
1475 u_char asr, csr, *msg; local
1891 wd33c93_nextstate(struct wd33c93_softc *sc, struct wd33c93_acb *acb, u_char csr, u_char asr) argument
2345 wd33c93_print_csr(u_char csr) argument
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/netbsd-6-1-5-RELEASE/sys/arch/pmax/pmax/
H A Ddec_3max.c130 uint32_t csr; local
153 csr = *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR);
154 csr &= ~(KN02_CSR_WRESERVED|KN02_CSR_IOINTEN|KN02_CSR_CORRECT|0xff);
155 *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR) = csr;
227 uint32_t csr; local
239 csr = *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR) &
241 csr |= (kn02intrs[i].intrbit << 16);
242 *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR) = csr;
256 uint32_t csr; local
262 csr
317 uint32_t erradr, csr; local
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H A Ddec_3100.c239 uint16_t csr; local
241 csr = *(volatile uint16_t *)MIPS_PHYS_TO_KSEG1(KN01_SYS_CSR);
243 if (csr & KN01_CSR_MERR) {
248 csr = (csr & ~KN01_CSR_MBZ) | 0xff;
249 *(volatile uint16_t *)MIPS_PHYS_TO_KSEG1(KN01_SYS_CSR) = csr;
/netbsd-6-1-5-RELEASE/sys/dev/sbus/
H A Dcs4231_sbus.c242 uint32_t csr; local
274 csr = bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, APC_DMA_CSR);
276 snprintb(bits, sizeof(bits), APC_BITS, csr);
278 DPRINTF(("trigger_output: csr=%s\n", bits));
279 if ((csr & PDMA_GO) == 0 || (csr & APC_PPAUSE) != 0) {
282 csr &= ~(APC_PPAUSE | APC_PMIE | APC_INTR_MASK);
283 bus_space_write_4(sbsc->sc_bt, sbsc->sc_bh, APC_DMA_CSR, csr);
285 csr = bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, APC_DMA_CSR);
286 csr
327 uint32_t csr; local
374 uint32_t csr; local
458 uint32_t csr; local
504 uint32_t csr; local
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H A Dif_le_ledma.c158 uint32_t csr; local
160 csr = L64854_GCSR(dma);
161 csr |= E_TP_AUI;
162 L64854_SCSR(dma, csr);
170 uint32_t csr; local
172 csr = L64854_GCSR(dma);
173 csr &= ~E_TP_AUI;
174 L64854_SCSR(dma, csr);
230 uint32_t csr; local
236 csr
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/netbsd-6-1-5-RELEASE/sys/arch/sun3/dev/
H A Ddma.c207 uint32_t csr; local
213 csr = DMA_GCSR(sc);
215 csr |= D_RESET; /* reset DMA */
216 DMA_SCSR(sc, csr);
220 csr = DMA_GCSR(sc);
221 csr &= ~D_RESET; /* de-assert reset line */
222 DMA_SCSR(sc, csr);
231 csr = DMA_GCSR(sc);
232 csr |= D_INT_EN; /* enable interrupts */
234 DMA_SCSR(sc, csr);
249 uint32_t csr; local
312 uint32_t csr; local
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H A Dmemerr.c68 const char *sc_csrbits; /* how to print csr bits */
162 uint8_t csr, ctx; local
167 csr = me->me_csr;
168 if ((csr & ME_CSR_IPEND) == 0)
181 snprintb(bits, sizeof(bits), sc->sc_csrbits, csr);
182 printf(" csr=%s\n", bits);
189 if (csr & ME_PAR_EMASK) {
200 if (csr & (ME_ECC_WBTMO | ME_ECC_WBERR)) {
204 if (csr & ME_ECC_UE) {
208 if (csr
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/netbsd-6-1-5-RELEASE/sys/arch/cobalt/stand/boot/
H A Dzs.c140 uint8_t csr; local
143 csr = zs_read(dev, ZS_CSR);
144 } while ((csr & ZSRR0_TX_READY) == 0);
152 uint8_t csr, data; local
155 csr = zs_read(dev, ZS_CSR);
156 } while ((csr & ZSRR0_RX_READY) == 0);
165 uint8_t csr, data; local
167 csr = zs_read(dev, ZS_CSR);
168 if ((csr & ZSRR0_RX_READY) == 0)
/netbsd-6-1-5-RELEASE/sys/arch/sh3/dev/
H A Dadc.c124 uint8_t csr; local
141 csr = ADC_(CSR);
142 if ((csr & SH7709_ADCSR_ADST) != 0) {
144 snprintb(bits, sizeof(bits), SH7709_ADCSR_BITS, csr);
158 csr = ADC_(CSR);
161 } while ((csr & SH7709_ADCSR_ADF) == 0);
164 csr &= ~(SH7709_ADCSR_ADF | SH7709_ADCSR_ADST);
165 ADC_(CSR) = csr;
/netbsd-6-1-5-RELEASE/sys/arch/hp300/dev/
H A Dhp98265reg.h52 #define SCSI_IPL(csr) ((((csr) >> 4) & 3) + 3)
/netbsd-6-1-5-RELEASE/sys/dev/vme/
H A Dsi.c367 uint16_t csr; local
373 csr = SIREG_READ(ncr_sc, SIREG_CSR);
375 NCR_TRACE("si_intr: csr=0x%x\n", csr);
377 if (csr & SI_CSR_DMA_CONFLICT) {
381 if (csr & SI_CSR_DMA_BUS_ERR) {
389 csr |= SI_CSR_DMA_IP;
392 if (csr & (SI_CSR_SBC_IP | SI_CSR_DMA_IP)) {
564 int tmo, csr_mask, csr; local
575 csr
611 uint16_t csr; local
633 uint16_t csr; local
658 uint16_t csr; local
732 uint16_t csr; local
799 uint16_t csr; local
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/netbsd-6-1-5-RELEASE/sys/arch/amiga/dev/
H A Dsbic.c188 csr_trace[csr_traceptr].whr = (w); csr_trace[csr_traceptr].csr = (c); \
199 u_char csr; member in struct:__anon5636
214 sbic_trace[sbic_traceptr].csr = csr_traceptr; \
227 int csr; member in struct:__anon5637
701 int csr; local
710 GET_SBIC_csr(regs, csr);
711 printf("sbicwait TIMEO @%d with asr=x%x csr=x%x\n",
712 line, val, csr);
729 u_char csr, asr; local
732 GET_SBIC_csr(regs, csr);
858 u_char csr; local
946 sbicerror(struct sbic_softc *dev, sbic_regmap_t regs, u_char csr) argument
970 u_char asr, csr, id; local
1236 u_char orig_csr, csr, asr; local
1312 u_char phase, csr, asr; local
1555 u_char phase, asr, csr; local
1599 u_char csr, asr, *addr; local
1814 u_char asr, csr; local
1861 u_char asr, csr; local
1922 u_char asr, csr, *tmpaddr; local
2190 sbicnextstate(struct sbic_softc *dev, u_char csr, u_char asr) argument
2614 u_char csr, asr; local
2681 u_char csr, asr; local
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/netbsd-6-1-5-RELEASE/sys/arch/acorn32/podulebus/
H A Dsbic.c100 * The UPROTECTED_CSR code is bogus. It can read the csr (SCSI Status
212 csr_trace[csr_traceptr].whr = (w); csr_trace[csr_traceptr].csr = (c); \
221 u_char csr; member in struct:__anon5558
236 sbic_trace[sbic_traceptr].csr = csr_traceptr; \
246 int csr; member in struct:__anon5559
612 int csr; local
621 GET_SBIC_csr(regs, csr);
622 printf("sbicwait TIMEO @%d with asr=x%x csr=x%x\n",
623 line, val, csr);
640 u_char csr, as local
785 u_char csr; local
883 sbicerror(struct sbic_softc *dev, sbic_regmap_p regs, u_char csr) argument
903 u_char asr, csr, id; local
1174 u_char orig_csr, csr; local
1251 u_char phase, csr, asr; local
1488 u_char phase, asr, csr; local
1535 u_char asr = 0, csr = 0; local
1649 u_char asr, csr; local
1700 u_char asr, csr; local
1764 u_char asr, csr, *tmpaddr; local
2025 sbicnextstate(struct sbic_softc *dev, u_char csr, u_char asr) argument
2360 u_char csr, asr; local
2425 u_char csr, asr; local
[all...]
/netbsd-6-1-5-RELEASE/sys/arch/sparc/dev/
H A Dsw.c400 u_short csr; local
406 csr = SWREG_READ(ncr_sc, SWREG_CSR);
408 NCR_TRACE("sw_intr: csr=0x%x\n", csr);
410 if (csr & SW_CSR_DMA_CONFLICT) {
414 if (csr & SW_CSR_DMA_BUS_ERR) {
422 csr |= SW_CSR_DMA_IP;
425 if (csr & (SW_CSR_SBC_IP | SW_CSR_DMA_IP)) {
591 int tmo, csr_mask, csr; local
602 csr
635 uint32_t csr; local
652 uint32_t csr; local
672 uint32_t csr; local
695 uint32_t csr; local
828 uint32_t csr; local
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/netbsd-6-1-5-RELEASE/sys/arch/evbarm/stand/boot2440/
H A Ddm9k.c65 unsigned int csr; member in struct:dm9k_sc
77 *(volatile uint8_t*)(sc->csr) = reg;
78 return *(volatile uint8_t*)(sc->csr+4);
84 *(volatile uint8_t *)(sc->csr) = reg;
85 return *(volatile uint16_t *)(sc->csr + 4);
91 *(volatile uint8_t *)(sc->csr) = reg;
92 *(volatile uint8_t *)(sc->csr + 4) = data;
98 *(volatile uint8_t *)(sc->csr) = reg;
99 *(volatile uint16_t *)(sc->csr + 4) = data;
113 sc.csr
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/netbsd-6-1-5-RELEASE/sys/arch/mvme68k/dev/
H A Dsbic.c729 int csr; local
730 GET_SBIC_csr(regs, csr);
731 printf("sbicwait TIMEO @%d with asr=x%x csr=x%x\n",
732 line, val, csr);
751 u_char csr, asr; local
754 GET_SBIC_csr(regs, csr);
756 printf ("%s: abort %s: csr = 0x%02x, asr = 0x%02x\n",
757 dev->sc_dev.dv_xname, where, csr, asr);
806 GET_SBIC_csr (regs, csr);
807 QPRINTF(("csr
880 u_char csr; local
929 sbicerror(struct sbic_softc *dev, u_char csr) argument
955 u_char target = dev->target, lun = dev->lun, asr, csr, id; local
1297 u_char csr, asr; local
1487 u_char phase, csr; local
1533 u_char csr, asr, *addr; local
1660 u_char asr, csr; local
1706 u_char asr, csr = SBIC_CSR_RESET; /* XXX: Quell un-init warning */ local
1775 u_char asr, csr, *tmpaddr, *msgaddr; local
2097 sbicnextstate(struct sbic_softc *dev, u_char csr, u_char asr) argument
[all...]
/netbsd-6-1-5-RELEASE/sys/arch/atari/pci/
H A Dpci_machdep.c96 u_int32_t csr; member in struct:pci_memreg
228 pcireg_t csr; local
243 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
244 csr &= ~(PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_IO_ENABLE);
245 csr &= ~PCI_COMMAND_MASTER_ENABLE;
246 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr);
285 if ((q != self) && (q->csr & what)) {
323 pcireg_t csr, address, mask; local
328 csr = 0;
345 csr
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H A Dpci_milan.c138 int i, csr; local
142 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
143 csr |= (PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_IO_ENABLE);
144 csr |= PCI_COMMAND_MASTER_ENABLE;
145 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr);
/netbsd-6-1-5-RELEASE/sys/arch/next68k/next68k/
H A Dclock.c100 timer->csr |= TIMER_REG_UPDATE;
132 timer->csr = 0;
135 timer->csr = TIMER_REG_ENABLE|TIMER_REG_UPDATE;
/netbsd-6-1-5-RELEASE/sys/dev/ebus/
H A Dcs4231_ebus.c294 u_int32_t csr; local
301 csr = bus_space_read_4(dt, dh, EBUS_DMAC_DCSR);
302 if ((csr & (EBDMA_CYC_PEND | EBDMA_DRAIN)) == 0)
308 snprintb(bits, sizeof(bits), EBUS_DCSR_BITS, csr);
309 printf("cs4231_ebus_dma_reset: timed out: csr=%s\n", bits);
313 bus_space_write_4(dt, dh, EBUS_DMAC_DCSR, csr & ~EBDMA_RESET);
349 uint32_t csr; local
363 csr = bus_space_read_4(dt, dh, EBUS_DMAC_DCSR);
365 csr | EBDMA_EN_NEXT | (iswrite ? EBDMA_WRITE : 0)
443 u_int32_t csr; local
467 uint32_t csr; local
490 uint32_t csr; local
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/netbsd-6-1-5-RELEASE/sys/arch/pmax/ibus/
H A Ddz_ibus.c119 uint16_t csr; /* 00 Csr: control/status */ member in struct:dzregs
189 dz->csr = DZ_CSR_MSE | DZ_CSR_TXIE;
244 unsigned csr; local
249 while (((csr = dzr->csr) & (DZ_CSR_RX_DONE | DZ_CSR_TX_READY)) != 0) {
250 if ((csr & DZ_CSR_RX_DONE) != 0)
252 if ((csr & DZ_CSR_TX_READY) != 0)
286 dzcn->csr = 0;
296 dzcn->csr = 0x20;
319 while ((dzcn->csr
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/netbsd-6-1-5-RELEASE/sys/arch/ews4800mips/sbd/
H A Dkbms_sbdio.c250 *csr = (r); \
252 *csr = (v); \
260 volatile uint8_t *csr = reg->kbd_csr; local
306 volatile uint8_t *csr = reg->kbd_csr; local
312 __RETRY_LOOP(*csr & ZSRR0_RX_READY, dummy = *data);
313 *csr = 48;
315 __RETRY_LOOP((*csr & ZSRR0_RX_READY) == 0, 0);
316 *csr = 1;
317 __RETRY_LOOP((*csr & (ZSRR1_FE | ZSRR1_DO | ZSRR1_PE)) != 0, 0);
319 __RETRY_LOOP((*csr
337 volatile uint8_t *csr = reg->mouse_csr; local
420 kbd_sbdio_cnattach(uint32_t csr, uint32_t data) argument
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