Searched refs:chip (Results 1 - 25 of 92) sorted by relevance

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/netbsd-6-1-5-RELEASE/sys/dev/pci/n8/common/
H A DcontextMem.h54 * 02/18/02 brr Support chip selection.
68 void N8_ContextMemInit (int chip);
69 void N8_ContextMemRemove(int chip);
70 void N8_ContextMemFreeAll(N8_Unit_t chip, unsigned long sessionID);
71 N8_Status_t n8_contextalloc(N8_Unit_t *chip,
75 n8_contextfree(int chip, unsigned long sessionID, unsigned long entry);
77 n8_contextvalidate(N8_Unit_t chip, unsigned long sessionID, unsigned int entry);
H A DcontextMem.c75 * 02/18/02 brr Support chip selection.
286 void N8_ContextMemInit(int chip) argument
290 NspInstance_t *NSPinstance_p = &NSPDeviceTable_g[chip];
293 printf("N8_ContextMemInit(chip=%d)\n", chip);
295 printf("N8_ContextMemInit(chip=%d): still ok\n", chip);
312 printf("N8_ContextMemInit(chip=%d): N8_AtomicLockInit\n", chip);
333 void N8_ContextMemRemove(int chip) argument
368 N8_ContextMemAlloc(N8_Unit_t *chip, unsigned int *index_p) argument
397 n8_contextalloc(N8_Unit_t *chip, unsigned long sessionID, unsigned int *index_p) argument
486 N8_ContextMemFree(int chip, unsigned long entry) argument
512 n8_contextfree(int chip, unsigned long sessionID, unsigned long entry) argument
561 N8_ContextMemValidate(N8_Unit_t chip, unsigned int entry) argument
588 n8_contextvalidate(N8_Unit_t chip, unsigned long sessionID, unsigned int entry) argument
644 N8_ContextMemFreeAll(N8_Unit_t chip, unsigned long sessionID) argument
687 int chip; local
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H A Dnsp_ioctl.c56 * 10/10/02 brr Modified diagnostic ioctl to accept chip number.
363 retval = waitOnInterrupt( parms.chip,
441 n8_contextalloc(&parms.chip,
455 retval = n8_contextfree(parms.chip, SessionID, parms.contextIndex);
466 retval = n8_contextvalidate(parms.chip, SessionID, parms.contextIndex);
638 int chip; local
641 chip = diagInfo.chip;
644 diagInfo.registerBase = NSPDeviceTable_g[chip].NSPregs_base;
645 diagInfo.registerSize = NSPDeviceTable_g[chip]
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H A Dirq.c428 reqsComplete = QMgrCheckQueue(N8_PKP, NSPinstance_p->chip,
433 QMgrCmdError(N8_PKP, NSPinstance_p->chip, readIndx, reg);
469 reqsComplete = QMgrCheckQueue(N8_PKP, NSPinstance_p->chip, cmdsComplete);
639 QMgrCheckQueue(N8_EA, NSPinstance_p->chip, cmdsComplete);
643 QMgrCmdError(N8_EA, NSPinstance_p->chip, readIndx, reg);
679 QMgrCheckQueue(N8_EA, NSPinstance_p->chip, cmdsComplete);
721 int waitOnInterrupt ( N8_Unit_t chip, argument
729 NspInstance_t *NSPinstance_p = &NSPDeviceTable_g[chip];
827 N8_Status_t N8_WaitOnInterrupt ( N8_Unit_t chip, argument
832 return waitOnInterrupt(chip, coretyp
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/netbsd-6-1-5-RELEASE/sys/arch/arm/gemini/
H A Dgemini_com.h9 # error unknown gemini chip
/netbsd-6-1-5-RELEASE/sys/arch/mips/sibyte/include/
H A Dsb1250_defs.h62 * for chip features only present in certain chip revisions.
64 * SIBYTE_HDR_FEATURES may be defined to be the mask value chip/revision
72 * Generate defines only for that revision of chip.
74 * #if SIBYTE_HDR_FEATURE(chip,pass)
77 * that particular chip type are enabled in SIBYTE_HDR_FEATURES.
81 * Note that there is no implied ordering between chip types.
83 * Note also that 'chip' and 'pass' must textually exactly
88 * #if SIBYTE_HDR_FEATURE_UP_TO(chip,pass)
91 * and earlier revisions of the named chip typ
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/netbsd-6-1-5-RELEASE/sys/dev/nand/
H A Dnand.c133 struct nand_chip *chip = &sc->sc_chip; local
142 aprint_error("NAND chip is write protected!\n");
146 if (nand_scan_media(self, chip)) {
150 nand_flash_if.erasesize = chip->nc_block_size;
151 nand_flash_if.page_size = chip->nc_page_size;
152 nand_flash_if.writesize = chip->nc_page_size;
155 chip->nc_oob_cache = kmem_alloc(chip->nc_spare_size, KM_SLEEP);
156 chip->nc_page_cache = kmem_alloc(chip
189 struct nand_chip *chip = &sc->sc_chip; local
223 struct nand_chip *chip = &sc->sc_chip; local
330 nand_fill_chip_structure_legacy(device_t self, struct nand_chip *chip) argument
347 nand_scan_media(device_t self, struct nand_chip *chip) argument
529 nand_fill_chip_structure(device_t self, struct nand_chip *chip) argument
592 struct nand_chip *chip = &sc->sc_chip; local
616 struct nand_chip *chip = &sc->sc_chip; local
663 struct nand_chip *chip = &sc->sc_chip; local
751 struct nand_chip *chip = &sc->sc_chip; local
819 struct nand_chip *chip = &sc->sc_chip; local
840 struct nand_chip *chip = &sc->sc_chip; local
866 struct nand_chip *chip = &sc->sc_chip; local
894 struct nand_chip *chip = &sc->sc_chip; local
931 struct nand_chip *chip = &sc->sc_chip; local
969 struct nand_chip *chip = &sc->sc_chip; local
1055 struct nand_chip *chip = &sc->sc_chip; local
1181 struct nand_chip *chip = &sc->sc_chip; local
1243 struct nand_chip *chip = &sc->sc_chip; local
1314 struct nand_chip *chip = &sc->sc_chip; local
1378 struct nand_chip *chip = &sc->sc_chip; local
1408 struct nand_chip *chip = &sc->sc_chip; local
1434 struct nand_chip *chip = &sc->sc_chip; local
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H A Dnand_micron.c92 nand_read_parameters_micron(device_t self, struct nand_chip * const chip) argument
99 KASSERT(chip->nc_manf_id == NAND_MFR_MICRON);
100 switch (chip->nc_manf_id) {
116 KASSERT(chip->nc_manf_id == mfgrid);
124 return mt29fxgx_parameters(self, chip, devid, params);
132 mt29fxgx_parameters(device_t self, struct nand_chip * const chip, argument
149 chip->nc_addr_cycles_column = 2; /* XXX */
150 chip->nc_addr_cycles_row = 3; /* XXX */
152 chip->nc_flags |= NC_BUSWIDTH_16;
153 chip
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H A Dnand_bbt.c51 struct nand_chip *chip = &sc->sc_chip; local
54 bbt->nbbt_size = chip->nc_size / chip->nc_block_size / 4;
73 struct nand_chip *chip = &sc->sc_chip; local
76 blocks = chip->nc_size / chip->nc_block_size;
88 addr += chip->nc_block_size;
101 struct nand_chip *chip = &sc->sc_chip; local
102 uint8_t *oob = chip->nc_oob_cache;
119 struct nand_chip *chip local
161 struct nand_chip *chip = &sc->sc_chip; local
205 struct nand_chip *chip = &sc->sc_chip; local
225 struct nand_chip *chip = &sc->sc_chip; local
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/netbsd-6-1-5-RELEASE/sys/dev/nor/
H A Dnor.c144 struct nor_chip * const chip = &sc->sc_chip; local
153 if (nor_scan_media(self, chip))
157 sc->sc_flash_if.erasesize = chip->nc_block_size;
158 sc->sc_flash_if.page_size = chip->nc_page_size;
159 sc->sc_flash_if.writesize = chip->nc_page_size;
163 chip->nc_oob_cache = kmem_alloc(chip->nc_spare_size, KM_SLEEP);
165 chip->nc_page_cache = kmem_alloc(chip->nc_page_size, KM_SLEEP);
191 kmem_free(chip
201 struct nor_chip * const chip = &sc->sc_chip; local
235 struct nor_chip * const chip = &sc->sc_chip; local
330 nor_quirks(device_t self, struct nor_chip * const chip) argument
351 nor_scan_media(device_t self, struct nor_chip * const chip) argument
424 struct nor_chip * const chip = &sc->sc_chip; local
463 struct nor_chip * const chip = &sc->sc_chip; local
519 struct nor_chip * const chip = &sc->sc_chip; local
597 struct nor_chip * const chip = &sc->sc_chip; local
725 struct nor_chip * const chip = &sc->sc_chip; local
789 struct nor_chip * const chip = &sc->sc_chip; local
861 struct nor_chip * const chip = &sc->sc_chip; local
927 struct nor_chip * const chip = &sc->sc_chip; local
963 struct nor_chip * const chip = &sc->sc_chip; local
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/netbsd-6-1-5-RELEASE/sys/dev/pci/n8/include_private/
H A Dn8_driver_api.h238 * @param chip RO: Chip number of chip we are waiting on.
258 extern N8_Status_t N8_WaitOnInterrupt( N8_Unit_t chip,
275 * selects which chip's queue to query via the chip
284 * N8_INVALID_PARAMETER Invalid chip selector.
334 * N8_INVALID_PARAMETER Invalid chip selector.
374 * @param chip RO: The chip.
385 extern N8_Status_t N8_ContextMemAlloc (N8_Unit_t *chip, unsigne
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H A Dnsp_ioctl.h117 N8_Unit_t chip; member in struct:__anon8061
H A Dn8_enqueue_common.h124 * 07/20/01 hml Added chip to the queue control.
130 * 06/15/01 hml added unit and chip to the API_Request_t structure.
205 * chip tells what chipset the request is for
219 int chip; member in struct:QMgrRequest_t
335 N8_Unit_t chip; member in struct:__anon8052
/netbsd-6-1-5-RELEASE/sys/dev/pci/n8/QMgr/
H A DQMUtil.c139 /* Requested an invalid chip/unit or passed a null pointer */
158 DBG(("QMgr_get_chip_for_request: providing chip %d.\n",
159 (*queue_pp)->chip));
169 * @brief Given a component type and a chip index, this function fetches the
175 * @param chip RO: The chip identifier.
182 * N8_INVALID_PARAMETER: The unit or chip is invalid or the input pointer
196 int chip)
198 if ((chip >= queueTable_g.nControlSets) ||
202 /* Requested an invalid chip/uni
194 QMgr_get_control_struct(QueueControl_t **queue_pp, N8_Component_t unit, int chip) argument
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H A DQMQueue.h152 * chip.
185 int chip; /**< Chip number for this queue. member in struct:QueueControl_s
242 * of a single nsp2000 chip.
271 int QMgrCheckQueue(N8_Component_t unit, int chip, uint16_t cmdsComplete);
273 int chip,
H A DQMUtil.h91 int chip);
/netbsd-6-1-5-RELEASE/sys/arch/hpcmips/tx/
H A Dtxcom.c199 struct txcom_chip *chip; local
211 printf(": can't allocate chip\n");
217 chip = sc->sc_chip;
218 tc = chip->sc_tc = ua->ua_tc;
219 slot = chip->sc_slot = ua->ua_slot;
222 txcom_dump(chip);
225 txcom_reset(chip);
240 if (ISSET(chip->sc_hwflags, TXCOM_HW_CONSOLE)) {
306 txcom_reset(struct txcom_chip *chip) argument
312 tc = chip
326 txcom_enable(struct txcom_chip *chip, bool console) argument
379 txcom_disable(struct txcom_chip *chip) argument
404 __txcom_txbufready(struct txcom_chip *chip, int retry) argument
421 struct txcom_chip *chip = sc->sc_chip; local
468 struct txcom_chip *chip = &txcom_chip; local
491 txcom_setmode(struct txcom_chip *chip) argument
534 txcom_setbaudrate(struct txcom_chip *chip) argument
587 struct txcom_chip *chip = sc->sc_chip; local
596 struct txcom_chip *chip = sc->sc_chip; local
694 struct txcom_chip *chip = sc->sc_chip; local
743 struct txcom_chip *chip = sc->sc_chip; local
782 struct txcom_chip *chip; local
1023 struct txcom_chip *chip; local
1064 struct txcom_chip *chip; local
1151 struct txcom_chip *chip = sc->sc_chip; local
1167 struct txcom_chip *chip = sc->sc_chip; local
1186 txcom_dump(struct txcom_chip *chip) argument
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H A Dtx3912video.c90 /* TX3912 built-in video chip itself */
132 struct video_chip *chip; local
145 sc->sc_chip = chip = &tx3912video_chip;
149 depth_print[(ffs(chip->vc_fbdepth) - 1) & 0x3],
150 (unsigned)chip->vc_fbpaddr,
151 (unsigned)(chip->vc_fbpaddr + chip->vc_fbsize));
154 tc = chip->vc_v;
207 struct video_chip *chip = sc->sc_chip; local
208 tx_chipset_tag_t tc = chip
238 struct video_chip *chip = sc->sc_chip; local
298 struct video_chip *chip = &tx3912video_chip; local
355 tx3912video_framebuffer_alloc(struct video_chip *chip, paddr_t fb_start, paddr_t *fb_end ) argument
393 tx3912video_framebuffer_init(struct video_chip *chip) argument
434 tx3912video_resolution_init(struct video_chip *chip) argument
471 tx3912video_reset(struct video_chip *chip) argument
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/netbsd-6-1-5-RELEASE/sys/arch/hpcmips/vr/
H A Dvrkiu.c102 vrkiu_write(struct vrkiu_chip *chip, int port, unsigned short val) argument
105 bus_space_write_2(chip->kc_iot, chip->kc_ioh, port, val);
109 vrkiu_read(struct vrkiu_chip *chip, int port) argument
112 return (bus_space_read_2(chip->kc_iot, chip->kc_ioh, port));
185 vrkiu_init(struct vrkiu_chip *chip, bus_space_tag_t iot, argument
189 memset(chip, 0, sizeof(struct vrkiu_chip));
190 chip->kc_iot = iot;
191 chip
252 eliminate_phantom_keys(struct vrkiu_chip *chip, unsigned short *scandata) argument
291 vrkiu_scan(struct vrkiu_chip* chip) argument
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/netbsd-6-1-5-RELEASE/sys/dev/isa/
H A Dcmsreg.h34 #define CMS_DATA0 0x00 /* for chip 0, voices 0-5 */
37 #define CMS_DATA1 0x02 /* for chip 1, voices 6-11 */
130 #define CMS_WRITE(sc, chip, reg, val) \
132 (sc)->sc_shadowregs[((chip)<<5) + (reg)] = val; \
134 CMS_ADDR0 + ((chip)<<1), (reg)); \
136 CMS_DATA0 + ((chip)<<1), (val)); \
139 #define CMS_READ(sc, chip, reg) ((sc)->sc_shadowregs[((chip)<<5) + (reg)])
H A Dcms.c68 /* shadow registers for each chip */
230 int chip = CHAN_TO_CHIP(vidx); local
257 DPRINTF(("chip=%d voice=%d octave=%d count=%d offset=%d shift=%d\n",
258 chip, voice, octave, count, OCTAVE_OFFSET(voice),
262 CMS_WRITE(sc, chip, CMS_IREG_FREQ0 + voice, count);
265 reg = CMS_READ(sc, chip, CMS_IREG_OCTAVE_1_0 + OCTAVE_OFFSET(voice));
268 CMS_WRITE(sc, chip, CMS_IREG_OCTAVE_1_0 + OCTAVE_OFFSET(voice), reg);
273 CMS_WRITE(sc, chip, CMS_IREG_VOL0 + voice, ((vol<<4)|vol));
276 reg = CMS_READ(sc, chip, CMS_IREG_FREQ_CTL);
278 CMS_WRITE(sc, chip, CMS_IREG_FREQ_CT
285 int chip = CHAN_TO_CHIP(vidx); local
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/netbsd-6-1-5-RELEASE/sys/dev/ic/
H A Dcyvar.h33 #define cd_read_reg(sc,chip,reg) bus_space_read_1(sc->sc_memt, \
34 sc->sc_bsh, sc->sc_cd1400_offs[chip] + \
37 #define cd_write_reg(sc,chip,reg,val) bus_space_write_1(sc->sc_memt, \
38 sc->sc_bsh, sc->sc_cd1400_offs[chip] + \
/netbsd-6-1-5-RELEASE/external/gpl3/gdb/dist/sim/testsuite/d10v-elf/
H A Dt-dbt.s7 ;;; Blat our DMAP registers so that they point at on-chip imem
/netbsd-6-1-5-RELEASE/sys/external/bsd/drm/dist/shared-core/
H A Dsavage_drv.h93 /* these chip tags should match the ones in the 2D driver in savage_regs.h. */
110 #define S3_SAVAGE3D_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE_MX))
112 #define S3_SAVAGE4_SERIES(chip) ((chip==S3_SAVAGE4) \
113 || (chip==S3_PROSAVAGE) \
114 || (chip==S3_TWISTER) \
115 || (chip==S3_PROSAVAGEDDR))
117 #define S3_SAVAGE_MOBILE_SERIES(chip) ((chi
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/netbsd-6-1-5-RELEASE/sys/dev/pci/n8/common/api/
H A Dn8_util.c98 * 07/20/01 bac Added chip id to calls to create[PK|EA]RequestBuffer.
215 const N8_Unit_t chip,
239 (*req_pp)->qr.chip = chip;
281 const N8_Unit_t chip,
290 req_p->qr.chip = chip;
337 const N8_Unit_t chip,
358 chip,
876 * @param chip R
214 createPKRequestBuffer(API_Request_t **req_pp, const N8_Unit_t chip, const unsigned int numCmds, const void *callbackFcn, const unsigned int dataBytes) argument
279 initializeEARequestBuffer(API_Request_t *req_p, N8_MemoryHandle_t *kmem_p, const N8_Unit_t chip, const unsigned int numCmds, const void *callbackFcn, N8_Boolean_t userRequest) argument
336 createEARequestBuffer(API_Request_t **req_pp, const N8_Unit_t chip, const unsigned int numCmds, const void *callbackFcn, const unsigned int dataBytes) argument
888 n8_validateUnit(N8_Unit_t chip) argument
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