Searched refs:ETH_CTL (Results 1 - 2 of 2) sorted by relevance

/netbsd-6-1-5-RELEASE/sys/arch/arm/at91/
H A Dat91emac.c160 EMAC_WRITE(ETH_CTL, 0); // disable everything
248 ctl = EMAC_READ(ETH_CTL); // get current control register value
249 EMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE); // disable receiver
251 EMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE); // re-enable receiver
346 EMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything
361 EMAC_WRITE(ETH_CTL, ETH_CTL_MPE);
483 EMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR
719 device_xname(sc->sc_dev), EMAC_READ(ETH_CTL), EMAC_READ(ETH_CFG));
736 EMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR
753 EMAC_WRITE(ETH_CTL, ETH_CTL_MP
[all...]
H A Dat91emacreg.h36 #define ETH_CTL 0x00U /* 0x00: Control Register */ macro

Completed in 62 milliseconds