Lines Matching refs:ETH_CTL
160 EMAC_WRITE(ETH_CTL, 0); // disable everything
248 ctl = EMAC_READ(ETH_CTL); // get current control register value
249 EMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE); // disable receiver
251 EMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE); // re-enable receiver
346 EMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything
361 EMAC_WRITE(ETH_CTL, ETH_CTL_MPE);
483 EMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR
719 device_xname(sc->sc_dev), EMAC_READ(ETH_CTL), EMAC_READ(ETH_CFG));
736 EMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR
753 EMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything
785 u_int32_t ctl = EMAC_READ(ETH_CTL);
789 EMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE);
884 EMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE);