Searched refs:EMAC_MR0 (Results 1 - 2 of 2) sorted by relevance

/netbsd-6-1-5-RELEASE/sys/arch/powerpc/ibm4xx/dev/
H A Dif_emac.c1029 EMAC_WRITE(sc, EMAC_MR0, MR0_TXE | MR0_RXE);
1071 EMAC_WRITE(sc, EMAC_MR0,
1072 EMAC_READ(sc, EMAC_MR0) & ~(MR0_TXE | MR0_RXE));
1350 EMAC_WRITE(sc, EMAC_MR0, MR0_SRST);
1359 while (EMAC_READ(sc, EMAC_MR0) & MR0_SRST) {
1374 mr0 = EMAC_READ(sc, EMAC_MR0);
1377 EMAC_WRITE(sc, EMAC_MR0, mr0);
1380 while ((EMAC_READ(sc, EMAC_MR0) & (MR0_TXI | MR0_RXI)) !=
1513 EMAC_WRITE(sc, EMAC_MR0, MR0_TXE | MR0_RXE);
H A Demacreg.h48 #define EMAC_MR0 0x00 /* Mode Register 0 */ macro

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