1/* $NetBSD: emacreg.h,v 1.2 2006/10/16 18:14:35 kiyohara Exp $ */ 2 3/* 4 * Copyright 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Simon Burge and Eduardo Horvath for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38#ifndef _IBM4XX_EMACREG_H_ 39#define _IBM4XX_EMACREG_H_ 40 41#define EMAC_MAX_MTU 9022 42 43 44/* Number of Ethernet MAC Registers */ 45#define EMAC_NREG 0x100 46 47/* Ethernet MAC Registers */ 48#define EMAC_MR0 0x00 /* Mode Register 0 */ 49#define MR0_RXI 0x80000000 /* Receive MAC Idle */ 50#define MR0_TXI 0x40000000 /* Transmit MAC Idle */ 51#define MR0_SRST 0x20000000 /* Soft Reset */ 52#define MR0_TXE 0x10000000 /* Transmit MAC Enable */ 53#define MR0_RXE 0x08000000 /* Receive MAC Enable */ 54#define MR0_WKE 0x04000000 /* Wake-up Enable */ 55 56#define EMAC_MR1 0x04 /* Mode Register 1 */ 57#define MR1_FDE 0x80000000 /* Full-Duplex Enable */ 58#define MR1_ILE 0x40000000 /* Internal Loop-back Enable */ 59#define MR1_VLE 0x20000000 /* VLAN Enable */ 60#define MR1_EIFC 0x10000000 /* Enable Integrated Flow Control */ 61#define MR1_APP 0x08000000 /* Allow Pause Packet */ 62#define MR1_IST 0x01000000 /* Ignore SQE Test */ 63#define MR1_MF_MASK 0x00c00000 /* Medium Frequency mask */ 64#define MR1_MF_10MBS 0x00000000 /* 10MB/sec */ 65#define MR1_MF_100MBS 0x00400000 /* 100MB/sec */ 66#define MR1_MF_1000MBS 0x00800000 /* 1000MB/sec */ 67#define MR1_RFS(fs) /* Receive FIFO size */ \ 68 (((fs) << 20) & 0x00300000) 69#define MR1_TFS(fs) /* Transmit FIFO size */ \ 70 (((fs) << 18) & 0x000c0000) 71#define MR1_RFS_GBE(fs) /* GbE's Receive FIFO size */ \ 72 (((fs) << 19) & 0x00380000) 73#define MR1_TFS_GBE(fs) /* GbE's Transmit FIFO size */ \ 74 (((fs) << 16) & 0x00070000) 75#define MR1__FS_512 0 76#define MR1__FS_1KB 1 77#define MR1__FS_2KB 2 78#define MR1__FS_4KB 3 79#define MR1__FS_8KB 4 80#define MR1__FS_16KB 5 81#define MR1_TR0_MASK 0x00018000 /* Transmit Request 0 */ 82#define MR1_TR0_SINGLE 0x00000000 /* Single Packet mode */ 83#define MR1_TR0_MULTIPLE 0x00008000 /* Multiple Packet mode */ 84#define MR1_TR0_DEPENDANT 0x00010000 /* Dependent Mode */ 85#define MR1_TR1_MASK 0x00006000 /* Transmit Request 1 */ 86#define MR1_TR1_SINGLE 0x00000000 /* Single Packet mode */ 87#define MR1_TR1_MULTIPLE 0x00002000 /* Multiply Packet mode */ 88#define MR1_TR1_DEPENDANT 0x00004000 /* Dependent Mode */ 89#define MR1_MWSW_MASK 0x00007000 /* Maximum Waiting Status Words (GbE) */ 90#define MR1_MWSW_SHIFT 12 91#define MR1_JPSM 0x00000800 /* Jumbo Packet Support Mode (GbE) */ 92#define MR1_IPPA_MASK 0x000007c0 /* Internal PCS PHY Address (GbE) */ 93#define MR1_IPPA_SHIFT 6 94#define MR1_OBCI(opbc) ((opbc) << 3) /* OPB Bus Clock Indication (GbE) */ 95 96#define EMAC_TMR0 0x08 /* Transmit Mode Register 0 */ 97#define TMR0_GNP0 0x80000000 /* Get New Packet for Channel 0 */ 98#define TMR0_GNP1 0x40000000 /* Get New Packet for Channel 1 */ 99#define TMR0_GNPD 0x20000000 /* Get New Packet for Dependent mode */ 100#define TMR0_FC_MASK 0x10000000 /* First Channel */ 101#define TMR0_FC_CHAN0 0x00000000 /* Channel 0 */ 102#define TMR0_FC_CHAN1 0x10000000 /* Channel 1 */ 103#define TMR0_TFAE_MASK 0x00000007 /* TX FIFO Almost Empty */ 104#define TMR0_TFAE_2 0x00000001 /* Number of used entries <= 2(32B) */ 105#define TMR0_TFAE_4 0x00000002 /* Number of used entries <= 4(64B) */ 106#define TMR0_TFAE_8 0x00000003 /* Number of used entries <= 8(128B) */ 107#define TMR0_TFAE_16 0x00000004 /* Number of used entries <= 16(256B) */ 108#define TMR0_TFAE_32 0x00000005 /* Number of used entries <= 32(512B) */ 109#define TMR0_TFAE_64 0x00000006 /* Number of used entries <= 64(1024B) */ 110#define TMR0_TFAE_128 0x00000007 /* Number of used entries <= 128(2048B) */ 111 112#define EMAC_TMR1 0x0c /* Transmit Mode Register 1 */ 113#define TMR1_TLR_MASK 0xf8000000 /* Transmit Low Request */ 114#define TMR1_TLR_SHIFT 27 115#define TMR1_TUR_MASK 0x00ff0000 /* Transmit Urgent Request */ 116#define TMR1_TUR_SHIFT 16 117 118#define EMAC_RMR 0x10 /* Receive Mode Register */ 119#define RMR_SP 0x80000000 /* Strip Padding */ 120#define RMR_SFCS 0x40000000 /* Strip FCS */ 121#define RMR_RRP 0x20000000 /* Receive Runt Packets */ 122#define RMR_RFP 0x10000000 /* Receive FCS Packets */ 123#define RMR_ROP 0x08000000 /* Receive Oversize Packets */ 124#define RMR_RPIR 0x04000000 /* Receive Packets with In Range Error */ 125#define RMR_PPP 0x02000000 /* Propagate Pause Packet */ 126#define RMR_PME 0x01000000 /* Promiscuous Mode Enable */ 127#define RMR_PMME 0x00800000 /* Promiscuous Multicast Mode Enable */ 128#define RMR_IAE 0x00400000 /* Individual Address Enable */ 129#define RMR_MIAE 0x00200000 /* Multiple Individual Address Enable */ 130#define RMR_BAE 0x00100000 /* Broadcast Address Enable */ 131#define RMR_MAE 0x00080000 /* Multicast Address Enable */ 132#define RMR_NIPMAE 0x00040000 /* Non-IP Multicast Address Enable */ 133#define RMR_RFAF_MASK 0x00000007 /* RX FIFO Almost Full - IRQ threshold */ 134#define RMR_TFAE_2 0x00000001 /* Number of used entries <= 2(32B) */ 135#define RMR_TFAE_4 0x00000002 /* Number of used entries <= 4(64B) */ 136#define RMR_TFAE_8 0x00000003 /* Number of used entries <= 8(128B) */ 137#define RMR_TFAE_16 0x00000004 /* Number of used entries <= 16(256B) */ 138#define RMR_TFAE_32 0x00000005 /* Number of used entries <= 32(512B) */ 139#define RMR_TFAE_64 0x00000006 /* Number of used entries <= 64(1024B) */ 140#define RMR_TFAE_128 0x00000007 /* Number of used entries <= 128(2048B) */ 141 142#define EMAC_ISR 0x14 /* Interrupt Status Register */ 143#define ISR_TXPE 0x20000000 /* TX Parity Error */ 144#define ISR_RXPE 0x10000000 /* RX Parity Error */ 145#define ISR_TXUE 0x08000000 /* TX Underrun Event */ 146#define ISR_RXOE 0x04000000 /* RX Overrun Event */ 147#define ISR_OVR 0x02000000 /* Overrun Error */ 148#define ISR_PP 0x01000000 /* Pause Packet */ 149#define ISR_BP 0x00800000 /* Bad Packet */ 150#define ISR_RP 0x00400000 /* Runt Packet */ 151#define ISR_SE 0x00200000 /* Short Event */ 152#define ISR_ALE 0x00100000 /* Alignment Error */ 153#define ISR_BFCS 0x00080000 /* Bad FCS */ 154#define ISR_PTLE 0x00040000 /* Packet Too Long Error */ 155#define ISR_ORE 0x00020000 /* Out of Range Error */ 156#define ISR_IRE 0x00010000 /* In Range Error */ 157#define ISR_DBDM 0x00000200 /* Dead Bit Dependent Mode */ 158#define ISR_DB0 0x00000100 /* Dead Bit 0 */ 159#define ISR_SE0 0x00000080 /* Signal Quality Error 0 (SQE) */ 160#define ISR_TE0 0x00000040 /* Transmit Error 0 */ 161#define ISR_DB1 0x00000020 /* Dead Bit 1 */ 162#define ISR_SE1 0x00000010 /* Signal Quality Error 1 */ 163#define ISR_TE1 0x00000008 /* Transmit Error 1 */ 164#define ISR_MOS 0x00000002 /* MMA Operation Succeeded */ 165#define ISR_MOF 0x00000001 /* MMA Operation Failed */ 166 167#define ISR_ALL ( ISR_TXPE| ISR_RXPE| \ 168 ISR_TXUE| ISR_RXOE| ISR_OVR | ISR_PP | \ 169 ISR_BP | ISR_RP | ISR_SE | ISR_ALE | \ 170 ISR_BFCS| ISR_PTLE| ISR_ORE | ISR_IRE | \ 171 ISR_DBDM| ISR_DB0 | \ 172 ISR_SE0 | ISR_TE0 | ISR_DB1 | ISR_SE1 | \ 173 ISR_TE1 | ISR_MOS | ISR_MOF) 174 175#define EMAC_ISER 0x18 /* Interrupt Status Enable Register */ 176#define ISER_TXPE ISR_TXPE 177#define ISER_RXPE ISR_RXPE 178#define ISER_TXUE ISR_TXUE 179#define ISER_RXOE ISR_RXOE 180#define ISER_OVR ISR_OVR 181#define ISER_PP ISR_PP 182#define ISER_BP ISR_BP 183#define ISER_RP ISR_RP 184#define ISER_SE ISR_SE 185#define ISER_ALE ISR_ALE 186#define ISER_BFCS ISR_BFCS 187#define ISER_PTLE ISR_PTLE 188#define ISER_ORE ISR_ORE 189#define ISER_IRE ISR_IRE 190#define ISER_DBDM ISR_DBDM 191#define ISER_DB0 ISR_DB0 192#define ISER_SE0 ISR_SE0 193#define ISER_TE0 ISR_TE0 194#define ISER_DB1 ISR_DB1 195#define ISER_SE1 ISR_SE1 196#define ISER_TE1 ISR_TE1 197#define ISER_MOS ISR_MOS 198#define ISER_MOF ISR_MOF 199 200#define EMAC_IAHR 0x1c /* Individual Address High Register */ 201#define EMAC_IALR 0x20 /* Individual Address Low Register */ 202#define EMAC_VTPID 0x24 /* VLAN TPID Register */ 203#define EMAC_VTCI 0x28 /* VLAN TCI Register */ 204#define EMAC_PTR 0x2c /* Pause Timer Register */ 205#define EMAC_NHT64 4 206#define EMAC_IAHT64(n) 0x30 /* 64b Individual Address Hash Table */ 207#define EMAC_GAHT64(n) 0x40 /* 64b Group Address Hash Table */ 208#define EMAC_LSAH 0x50 /* Last Source Address High */ 209#define EMAC_LSAL 0x54 /* Last Source Address Low */ 210#define EMAC_IPGVR 0x58 /* Inter-Packet Gap Value Register */ 211 212#define EMAC_STACR 0x5c /* STA Control Register */ 213#define STACR_PHYD 0xffff0000 /* PHY data mask */ 214#define STACR_PHYD_SHIFT 16 215#define STACR_OC 0x00008000 /* operation complete */ 216#define STACR_PHYE 0x00004000 /* PHY error */ 217#define STACR_WRITE 0x00002000 /* STA command - write */ 218#define STACR_READ 0x00001000 /* STA command - read */ 219#define STACR_OPBC_50MHZ 0x0 /* - 50MHz */ 220#define STACR_OPBC_66MHZ 0x1 /* - 66MHz */ 221#define STACR_OPBC_83MHZ 0x2 /* - 83MHz */ 222#define STACR_OPBC_100MHZ 0x3 /* - 100MHz */ 223#define STACR_OPBC_A100MHZ 0x4 /* - Abobe 100MHz (GbE) */ 224#define STACR_OPBC(opbc) ((opbc) << 10) /* OPB bus clock freq (!GbE)*/ 225#define STACR_PCDA 0x000003e0 /* PHY cmd dest address mask */ 226#define STACR_PCDA_SHIFT 5 227#define STACR_PRA 0x0000001f /* PHY register address mask */ 228#define STACR_PRA_SHIFT 0 229 230#define STACR_IMS 0x00002000 /* Indirect Mode Selection (405EX/440SPe) */ 231#define STACR_STAOPC_MASK 0x00001800 /* STA Opcode (405EX/440SPe) */ 232#define STACR_STAOPC_ADDRESS 0x00000000 /* (IMS=1) Address */ 233#define STACR_STAOPC_WRITE 0x00000800 /* Write */ 234#define STACR_STAOPC_READ 0x00001000 /* Read */ 235#define STACR_STAOPC_READINC 0x00001800 /* (IMS=1) Read Inc. */ 236 237#define EMAC_TRTR 0x60 /* Transmit Request Threshold Register */ 238#define TRTR_64 0x00000000 /* 64 bytes */ 239#define TRTR_128 0x08000000 /* 128 bytes */ 240#define TRTR_192 0x10000000 /* 192 bytes */ 241#define TRTR_256 0x18000000 /* 256 bytes */ 242/* ... and so on +64 until ... */ 243#define TRTR_2048 0xf8000000 /* 2048 bytes */ 244 245#define EMAC_RWMR 0x64 /* Receive Low/High Water Mark Register */ 246#define RWMR_RLWM_MASK 0xff800000 /* Receive Low Water Mark */ 247#define RWMR_RLWM_SHIFT 23 248#define RWMR_RHWM_MASK 0x0000ff80 /* Receive High Water Mark */ 249#define RWMR_RHWM_SHIFT 7 250 251#define EMAC_OCTX 0x68 /* Number of Octets Transmitted */ 252#define EMAC_OCRX 0x6c /* Number of Octets Received */ 253 254#define EMAC_IPCR 0x70 /* Internal PCS Configuration Register */ 255#define IPCR_OUI_MASK 0xfffffc00 /* OUI Value */ 256#define IPCR_OUI_SHIFT 10 257#define IPCR_MMN_MASK 0x000003f0 /* Manufacture Model Number */ 258#define IPCR_MMN_SHIFT 4 259#define IPCR_REVID_MASK 0x0000000f /* Revision Number */ 260#define IPCR_REVID_SHIFT 0 261 262#define EMAC_REVID 0x74 /* Revision ID Register */ 263#define REVID_REVISION(v) (((v) >> 8) & 0xfff) /* Revision */ 264#define REVID_BRANCHREV(v) ((v) & 0xff) /* Branch Revision */ 265 266#define EMAC_NHT256 8 267#define EMAC_IAHT256(n) 0x80 /* 256b Individual Address Hash Table */ 268#define EMAC_GAHT256(n) 0xa0 /* 256b Group Address Hash Table */ 269 270#define EMAC_TPC 0xc0 /* Transmit Pause Control Register */ 271#define TPC_IPA 0x80000000 /* Issue a Pause Packet */ 272#define TPC_TV_MASK 0x7fff8000 /* Timer Value */ 273#define TPC_TV_SHIFT 15 274 275#endif /* _IBM4XX_EMACREG_H_ */ 276