/netbsd-6-1-5-RELEASE/sys/dev/ic/ |
H A D | pca9564.c | 59 #define CSR_READ(sc, r) (*sc->sc_ios.read_byte)(sc->sc_dev, r) macro 129 control = CSR_READ(sc, PCA9564_I2CCON); 147 control = CSR_READ(sc, PCA9564_I2CCON); 161 DPRINTF(("%s: status=%#x\n", __func__, CSR_READ(sc, PCA9564_I2CSTA))); 163 if (CSR_READ(sc, PCA9564_I2CCON) & I2CCON_SI) 167 DPRINTF(("%s: status=%#x\n", __func__, CSR_READ(sc, PCA9564_I2CSTA))); 181 DPRINTF(("%s: status=%#x\n", __func__, CSR_READ(sc, PCA9564_I2CSTA))); 182 control = CSR_READ(sc, PCA9564_I2CCON); 186 DPRINTF(("%s: status=%#x\n", __func__, CSR_READ(sc, PCA9564_I2CSTA))); 197 DPRINTF(("%s: status=%#x\n", __func__, CSR_READ(s [all...] |
H A D | dp83932.c | 582 isr = CSR_READ(sc, SONIC_ISR) & sc->sc_imr; 1070 if ((CSR_READ(sc, SONIC_CR) & (CR_TXP|CR_RXEN|CR_ST)) == 0) 1074 if ((CSR_READ(sc, SONIC_CR) & (CR_TXP|CR_RXEN|CR_ST)) != 0) 1251 if ((CSR_READ(sc, SONIC_CR) & CR_LCAM) == 0) 1255 if (CSR_READ(sc, SONIC_CR) & CR_LCAM)
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H A D | dp83932var.h | 205 #define CSR_READ(sc, reg) \ macro
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/netbsd-6-1-5-RELEASE/sys/arch/cobalt/stand/boot/ |
H A D | ns16550.c | 39 #define CSR_READ(base, reg) (*(volatile uint8_t *)((base) + (reg))) macro 71 while ((CSR_READ(com_port, com_lsr) & LSR_TXRDY) == 0) 82 while ((CSR_READ(com_port, com_lsr) & LSR_RXRDY) == 0) 85 return CSR_READ(com_port, com_data); 93 if ((CSR_READ(com_port, com_lsr) & LSR_RXRDY) == 0) 96 return CSR_READ(com_port, com_data);
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H A D | lcd.c | 40 #define CSR_READ(base, reg) \
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H A D | tlp.c | 56 #define CSR_READ(l, r) (*(volatile uint32_t *)((l)->csr + (r))) macro 197 val = CSR_READ(l, TLP_BMR); 202 (void)CSR_READ(l, TLP_BMR); 423 ret = (ret << 1) | !!(CSR_READ(l, TLP_APROM) & VV);
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/netbsd-6-1-5-RELEASE/sys/arch/mmeye/stand/boot/ |
H A D | com.c | 102 #define CSR_READ(base, reg) (*(volatile uint8_t *)((base) + (reg))) macro 162 while ((CSR_READ(com_port, com_lsr) & LSR_TXRDY) == 0) 173 while ((CSR_READ(com_port, com_lsr) & LSR_RXRDY) == 0) 176 return CSR_READ(com_port, com_data); 184 if ((CSR_READ(com_port, com_lsr) & LSR_RXRDY) == 0) 187 return CSR_READ(com_port, com_data);
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/netbsd-6-1-5-RELEASE/sys/arch/sandpoint/stand/altboot/ |
H A D | sme.c | 47 #define CSR_READ(l, r) in32rb((l)->csr+(r)) macro 132 mac32 = CSR_READ(l, ADDRL); 133 mac16 = CSR_READ(l, ADDRH); 281 ctl = CSR_READ(l, MIIADDR); 286 ctl = CSR_READ(l, MIIADDR); 288 return CSR_READ(l, MIIDATA); 297 ctl = CSR_READ(l, MIIADDR);
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H A D | tlp.c | 47 #define CSR_READ(l, r) in32rb((l)->csr+(r)) macro 144 } while (i-- > 0 && (CSR_READ(l, PAR_CSR0) & PAR_SWR) != 0); 153 val = CSR_READ(l, PAR0_CSR25); 158 val = CSR_READ(l, PAR1_CSR26); 169 val = CSR_READ(l, AN_OMODE); 315 rv = (rv << 1) | !!(CSR_READ(l, SPR_CSR9) & MII_MDI);
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H A D | wm.c | 49 #define CSR_READ(l, r) in32rb((l)->csr+(r)) macro 312 v = CSR_READ(l, WMREG_EECD) & ~(EECD_SK | EECD_DI); 338 data = (data << 1) | !!(CSR_READ(l, WMREG_EECD) & EECD_DO); 343 v = CSR_READ(l, WMREG_EECD) & ~EECD_CS; 361 data = CSR_READ(l, WMREG_MDIC); 374 data = CSR_READ(l, WMREG_MDIC);
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H A D | sip.c | 47 #define CSR_READ(l, r) in32rb((l)->csr+(r)) macro 154 val = CSR_READ(l, SIP_CR); 187 val = CSR_READ(l, SIP_CFG); 328 data = (data << 1) | !!(CSR_READ(l, SIP_MEAR) & MEAR_EEDO); 361 val = CSR_READ(l, SIP_BMCR + (reg << 2));
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/netbsd-6-1-5-RELEASE/sys/dev/pci/ |
H A D | if_wm.c | 406 #define CSR_READ(sc, reg) \ macro 411 (void) CSR_READ((sc), WMREG_STATUS) 1067 if (CSR_READ(sc, reg) & SCTL_CTL_READY) 1092 reg = CSR_READ(sc, WMREG_EECD); 1296 sc->sc_funcid = (CSR_READ(sc, WMREG_STATUS) 1339 reg = CSR_READ(sc, WMREG_STATUS); 1493 CSR_READ(sc, WMREG_COLC); 1494 CSR_READ(sc, WMREG_RXERRC); 1541 reg = CSR_READ(sc, WMREG_EECD); 1552 reg = CSR_READ(s [all...] |
H A D | if_dge.c | 366 #define CSR_READ(sc, reg) \ macro 714 reg = CSR_READ(sc, DGE_STATUS); 1483 icr = CSR_READ(sc, DGE_ICR); 1786 status = CSR_READ(sc, DGE_STATUS); 1820 if ((CSR_READ(sc, DGE_CTRL0) & CTRL0_RST) == 0) 1825 if (CSR_READ(sc, DGE_CTRL0) & CTRL0_RST) 1954 reg = CSR_READ(sc, DGE_RXCSUM); 2240 hash = CSR_READ(sc, DGE_MTA + (reg << 2)); 2287 reg = CSR_READ(sc, DGE_EECD) & ~(EECD_SK|EECD_DI|EECD_CS); 2323 reg = CSR_READ(s [all...] |
/netbsd-6-1-5-RELEASE/sys/arch/mac68k/obio/ |
H A D | if_sn_obio.c | 207 i = CSR_READ(sc, SONIC_CAP2); 213 i = CSR_READ(sc, SONIC_CAP1); 219 i = CSR_READ(sc, SONIC_CAP0);
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/netbsd-6-1-5-RELEASE/sys/arch/sandpoint/sandpoint/ |
H A D | satmgr.c | 170 #define CSR_READ(t,r) bus_space_read_1((t)->sc_iot, (t)->sc_ioh, (r)) macro 430 lsr = CSR_READ(sc, LSR); 617 iir = CSR_READ(sc, IIR) & IIR_IMASK; 635 iir = CSR_READ(sc, IIR) & IIR_IMASK; 646 lsr = CSR_READ(sc, LSR); 652 (void) CSR_READ(sc, RBR); 654 lsr = CSR_READ(sc, LSR); 657 ch = CSR_READ(sc, RBR); 664 lsr = CSR_READ(sc, LSR); 920 lsr = CSR_READ(s [all...] |
/netbsd-6-1-5-RELEASE/sys/arch/evbarm/stand/boot2440/ |
H A D | main.c | 44 #define CSR_READ(reg) \ macro 460 stat = CSR_READ(S3C2440_UART_BASE(0) + SSCOM_UTRSTAT);
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