Lines Matching refs:CSR_READ
406 #define CSR_READ(sc, reg) \
411 (void) CSR_READ((sc), WMREG_STATUS)
1067 if (CSR_READ(sc, reg) & SCTL_CTL_READY)
1092 reg = CSR_READ(sc, WMREG_EECD);
1296 sc->sc_funcid = (CSR_READ(sc, WMREG_STATUS)
1339 reg = CSR_READ(sc, WMREG_STATUS);
1493 CSR_READ(sc, WMREG_COLC);
1494 CSR_READ(sc, WMREG_RXERRC);
1541 reg = CSR_READ(sc, WMREG_EECD);
1552 reg = CSR_READ(sc, WMREG_EECD);
1736 eeprom_data = CSR_READ(sc, WMREG_WUC);
1841 (CSR_READ(sc, WMREG_STATUS) & STATUS_TBIMODE) != 0) {
1853 reg = CSR_READ(sc, WMREG_CTRL_EXT);
2377 if (CSR_READ(sc, WMREG_TDT) == CSR_READ(sc, WMREG_TDH) &&
2378 CSR_READ(sc, WMREG_TDFT) == CSR_READ(sc, WMREG_TDFH) &&
2379 CSR_READ(sc, WMREG_TDFTS) == CSR_READ(sc, WMREG_TDFHS)) {
2385 uint32_t tctl = CSR_READ(sc, WMREG_TCTL);
2414 reg = CSR_READ(sc, WMREG_EXTCNFCTR);
3410 icr = CSR_READ(sc, WMREG_ICR);
3854 status = CSR_READ(sc, WMREG_STATUS);
3865 sc->sc_ctrl = CSR_READ(sc, WMREG_CTRL);
3930 WM_EVCNT_ADD(&sc->sc_ev_rx_xon, CSR_READ(sc, WMREG_XONRXC));
3931 WM_EVCNT_ADD(&sc->sc_ev_tx_xon, CSR_READ(sc, WMREG_XONTXC));
3932 WM_EVCNT_ADD(&sc->sc_ev_rx_xoff, CSR_READ(sc, WMREG_XOFFRXC));
3933 WM_EVCNT_ADD(&sc->sc_ev_tx_xoff, CSR_READ(sc, WMREG_XOFFTXC));
3934 WM_EVCNT_ADD(&sc->sc_ev_rx_macctl, CSR_READ(sc, WMREG_FCRUC));
3937 ifp->if_collisions += CSR_READ(sc, WMREG_COLC);
3939 + CSR_READ(sc, WMREG_CRCERRS)
3940 + CSR_READ(sc, WMREG_ALGNERRC)
3941 + CSR_READ(sc, WMREG_SYMERRC)
3942 + CSR_READ(sc, WMREG_RXERRC)
3943 + CSR_READ(sc, WMREG_SEC)
3944 + CSR_READ(sc, WMREG_CEXTERR)
3945 + CSR_READ(sc, WMREG_RLEC);
3946 ifp->if_iqdrops += CSR_READ(sc, WMREG_MPC) + CSR_READ(sc, WMREG_RNBC);
4034 if ((CSR_READ(sc, WMREG_STATUS) & STATUS_GIO_M_ENA) == 0)
4063 reg = CSR_READ(sc, WMREG_EXTCNFCTR)
4068 reg = CSR_READ(sc, WMREG_EXTCNFCTR);
4087 CSR_READ(sc, WMREG_CTRL) | CTRL_PHY_RESET);
4120 reg = CSR_READ(sc, WMREG_CTRL) | CTRL_RST;
4130 reg = CSR_READ(sc, WMREG_CTRL) | CTRL_RST;
4137 && ((CSR_READ(sc, WMREG_FWSM) & FWSM_FW_VALID)
4168 CSR_WRITE(sc, WMREG_CTRL, CSR_READ(sc, WMREG_CTRL) | CTRL_RST);
4182 reg = CSR_READ(sc, WMREG_CTRL_EXT) | CTRL_EXT_EE_RST;
4208 reg = CSR_READ(sc, WMREG_CTRL_EXT) | CTRL_EXT_EE_RST;
4252 if ((CSR_READ(sc, WMREG_EECD) & EECD_EE_PRES) == 0) {
4275 reg = CSR_READ(sc, WMREG_ICR);
4278 sc->sc_ctrl = CSR_READ(sc, WMREG_CTRL);
4350 ifp->if_collisions += CSR_READ(sc, WMREG_COLC);
4351 ifp->if_ierrors += CSR_READ(sc, WMREG_RXERRC);
4379 reg = CSR_READ(sc, WMREG_CTRL_EXT);
4569 val = CSR_READ(sc, WMREG_CTRL_EXT);
4589 reg = CSR_READ(sc, WMREG_RXCSUM);
4615 reg = CSR_READ(sc, WMREG_KABGTXD);
4671 reg = CSR_READ(sc, WMREG_TCTL_EXT);
4863 if (CSR_READ(sc, WMREG_EECD) & EECD_EE_AUTORD)
4889 reg = CSR_READ(sc, WMREG_STATUS);
4953 if (CSR_READ(sc, WMREG_EEMNGCTL) & mask)
4968 reg = CSR_READ(sc, WMREG_STATUS);
5014 reg = CSR_READ(sc, WMREG_EECD);
5022 reg = CSR_READ(sc, WMREG_EECD);
5060 reg = CSR_READ(sc, WMREG_EECD);
5084 reg = CSR_READ(sc, WMREG_EECD);
5111 reg = CSR_READ(sc, WMREG_EECD) & ~EECD_DI;
5117 if (CSR_READ(sc, WMREG_EECD) & EECD_DO)
5138 reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_DI);
5173 reg = CSR_READ(sc, WMREG_EECD) & ~EECD_CS;
5218 reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_CS);
5244 reg = (CSR_READ(sc, WMREG_EECD) & ~EECD_SK) | EECD_CS;
5352 data[i] = (CSR_READ(sc, WMREG_EERD) >> EERD_DATA_SHIFT);
5366 reg = CSR_READ(sc, rw);
5699 hash = CSR_READ(sc, mta_reg + (reg << 2));
5704 bit = CSR_READ(sc, mta_reg + ((reg - 1) << 2));
5792 status = CSR_READ(sc, WMREG_STATUS);
5800 if (CSR_READ(sc, WMREG_STATUS) & STATUS_FD)
5802 ctrl = CSR_READ(sc, WMREG_CTRL);
5845 i = CSR_READ(sc, WMREG_CTRL) & CTRL_SWDPIN(1);
5869 if (CSR_READ(sc, WMREG_STATUS) & STATUS_LU)
5876 status = CSR_READ(sc, WMREG_STATUS);
5891 sc->sc_ctrl = CSR_READ(sc, WMREG_CTRL);
5900 if (CSR_READ(sc, WMREG_CTRL) & CTRL_TFCE)
5959 status = CSR_READ(sc, WMREG_STATUS);
5961 rxcw = CSR_READ(sc, WMREG_RXCW);
5962 ctrl = CSR_READ(sc, WMREG_CTRL);
6073 reg = CSR_READ(sc, WMREG_CTRL_EXT);
6352 ctrl_ext = CSR_READ(sc, WMREG_CTRL_EXT);
6481 v = CSR_READ(sc, WMREG_CTRL);
6504 v = CSR_READ(sc, WMREG_CTRL);
6519 if (CSR_READ(sc, WMREG_CTRL) & MDI_IO)
6592 mdic = CSR_READ(sc, WMREG_MDIC);
6633 mdic = CSR_READ(sc, WMREG_MDIC);
6970 i2ccmd = CSR_READ(sc, WMREG_I2CCMD);
7013 i2ccmd = CSR_READ(sc, WMREG_I2CCMD);
7170 rv = CSR_READ(sc, WMREG_KUMCTRLSTA) & KUMCTRLSTA_MASK;
7220 eecd = CSR_READ(sc, WMREG_EECD);
7241 swsm = CSR_READ(sc, WMREG_SWSM);
7245 swsm = CSR_READ(sc, WMREG_SWSM);
7267 swsm = CSR_READ(sc, WMREG_SWSM);
7289 swfw_sync = CSR_READ(sc, WMREG_SW_FW_SYNC);
7315 swfw_sync = CSR_READ(sc, WMREG_SW_FW_SYNC);
7329 ext_ctrl = CSR_READ(sc, WMREG_EXTCNFCTR);
7333 ext_ctrl = CSR_READ(sc, WMREG_EXTCNFCTR);
7347 ext_ctrl = CSR_READ(sc, WMREG_EXTCNFCTR);
7360 *bank = (CSR_READ(sc, WMREG_EECD) & EECD_SEC1VAL) ? 1 : 0;
7700 fwsm = CSR_READ(sc, WMREG_FWSM);
7726 fwsm = CSR_READ(sc, WMREG_FWSM);
7742 manc = CSR_READ(sc, WMREG_MANC);
7751 fwsm = CSR_READ(sc, WMREG_FWSM);
7752 factps = CSR_READ(sc, WMREG_FACTPS);
7775 reg = CSR_READ(sc, WMREG_FWSM);
7787 reg = CSR_READ(sc, WMREG_MANC);
7808 reg = CSR_READ(sc, WMREG_SWSM);
7821 reg = CSR_READ(sc, WMREG_CTRL_EXT);
7838 reg = CSR_READ(sc, WMREG_SWSM);
7842 reg = CSR_READ(sc, WMREG_CTRL_EXT);
7857 rxcw = CSR_READ(sc, WMREG_RXCW);
7858 ctrl = CSR_READ(sc, WMREG_CTRL);
7859 status = CSR_READ(sc, WMREG_STATUS);
7950 reg = CSR_READ(sc, WMREG_PHY_CTRL);
7990 reg = CSR_READ(sc, WMREG_PHY_CTRL);
8116 ctrl = CSR_READ(sc, WMREG_CTRL);
8117 ctrl_ext = CSR_READ(sc, WMREG_CTRL_EXT);
8136 fwsm = CSR_READ(sc, WMREG_FWSM);
8162 gcr = CSR_READ(sc, WMREG_GCR);
8222 uint32_t manc2h = CSR_READ(sc, WMREG_MANC2H);
8223 uint32_t manc = CSR_READ(sc, WMREG_MANC);
8245 uint32_t manc = CSR_READ(sc, WMREG_MANC);
8277 if ((CSR_READ(sc, WMREG_FWSM) & FWSM_MODE_MASK) != 0)
8362 reg = CSR_READ(sc, WMREG_PHY_CTRL);
8386 reg = CSR_READ(sc, WMREG_CTRL_EXT);
8391 reg = CSR_READ(sc, WMREG_WUFC) | WUFC_MAG;
8394 CSR_WRITE(sc, WMREG_RCTL, CSR_READ(sc, WMREG_RCTL) | RCTL_MPE);
8452 ipcnfg = CSR_READ(sc, WMREG_IPCNFG);
8453 eeer = CSR_READ(sc, WMREG_EEER);
8467 CSR_READ(sc, WMREG_IPCNFG); /* XXX flush? */
8468 CSR_READ(sc, WMREG_EEER); /* XXX flush? */