/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/ARM/ |
H A D | ARMSelectionDAGInfo.h | 26 case ISD::SHL: return ARM_AM::lsl;
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H A D | ARMBaseInstrInfo.cpp | 2377 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))) 2393 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))) 2421 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))) 2434 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))) 2486 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))) 3083 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)) 3091 // Thumb2 mode: lsl only. 3111 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))) 3122 // Thumb2 mode: lsl only. 3384 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)) [all...] |
H A D | ARMISelDAGToDAG.cpp | 383 return ShOpcVal == ARM_AM::lsl && 506 ARM_AM::lsl), 605 ARM_AM::lsl), 1292 if (ShOpcVal != ARM_AM::lsl) { 1294 if (ShOpcVal == ARM_AM::lsl) 1298 if (ShOpcVal == ARM_AM::lsl) { 2181 case ARM_AM::lsl: Opc = ARM::t2MOVCClsl; break; 2537 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm); 2553 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
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H A D | ARMCodeEmitter.cpp | 412 case ARM_AM::lsl: return 0; 944 case ARM_AM::lsl: SBits = 0x1; break; 958 case ARM_AM::lsl: SBits = 0x0; break;
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/macosx-10.9.5/JavaScriptCore-7537.78.1/assembler/ |
H A D | MacroAssemblerARM.cpp | 76 op2 = m_assembler.lsl(address.index, static_cast<int>(address.scale)); 93 m_assembler.orr(dest, dest, m_assembler.lsl(ARMRegisters::S0, 16));
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H A D | ARMAssembler.cpp | 293 ARMWord op2 = lsl(index, scale); 343 ARMWord op2 = lsl(index, scale); 390 add(ARMRegisters::S1, base, lsl(index, scale));
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H A D | MacroAssemblerARM.h | 177 m_assembler.movs(dest, m_assembler.lsl(dest, imm.m_value & 0x1f)); 182 m_assembler.movs(dest, m_assembler.lsl(src, imm.m_value & 0x1f)); 958 m_assembler.add(ARMRegisters::pc, ARMRegisters::pc, m_assembler.lsl(index, scale));
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H A D | MacroAssemblerARMv7.h | 285 m_assembler.lsl(dest, src, dataTempRegister); 290 m_assembler.lsl(dest, src, imm.m_value & 0x1f);
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H A D | ARMAssembler.h | 656 static ARMWord lsl(int reg, ARMWord value) function in class:JSC::ARMAssembler
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMAddressingModes.h | 30 lsl, enumerator in enum:llvm::ARM_AM::ShiftOpc 49 case ARM_AM::lsl: return "lsl"; 60 case ARM_AM::lsl: return 0; 105 // reg [asr|lsl|lsr|ror|rrx] reg 106 // reg [asr|lsl|lsr|ror|rrx] imm
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H A D | ARMMCCodeEmitter.cpp | 185 case ARM_AM::lsl: return 0; 1168 case ARM_AM::lsl: SBits = 0x1; break; 1212 case ARM_AM::lsl: SBits = 0x0; break; 1327 case ARM_AM::lsl: SBits = 0x0; break;
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/macosx-10.9.5/swig-10/Lib/ocaml/ |
H A D | swigp4.ml | 61 | e1 = expr ; "'" ; "lsl" ; e2 = expr -> 99 | e1 = expr ; "'" ; "lsl" ; "=" ; e2 = expr ->
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/macosx-10.9.5/Csu-79/ |
H A D | start.s | 193 add r2, r1, r4, lsl #2 // get address of env[0] into r2
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/macosx-10.9.5/cxxfilt-11/cxxfilt/include/opcode/ |
H A D | avr.h | 170 AVR_INSN (lsl, "r=r", "000011rdddddrrrr", 1, AVR_ISA_1200, 0x0c00)
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/macosx-10.9.5/objc4-551.1/runtime/ |
H A D | a1a2-blocktramps-arm.s | 48 lsl r1, r1, #20
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H A D | a2a3-blocktramps-arm.s | 46 lsl r2, r2, #20
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/macosx-10.9.5/dyld-239.4/src/ |
H A D | dyldStartup.s | 309 add r2, r1, r0, lsl #2
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/macosx-10.9.5/zsh-60/zsh/Src/Zle/ |
H A D | compctl.c | 1726 static int lpl, lsl, rpl, rsl, fpl, fsl, lppl, lpsl; variable 3159 lsl = strlen(lsuf); 3376 p = (char *) zhalloc(lpl + lsl + 3); 3381 if (*lsuf && lsuf[lsl - 1] != '*' && lsuf[lsl - 1] != ')')
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H A D | compcore.c | 2027 int lpl, lsl, pl, sl, bcp = 0, bcs = 0, bpadd = 0, bsadd = 0; local 2216 lsl = strlen(dat->psuf); 2218 lsl = 0; 2284 if (llsl <= lsl && strsfx(lsuf, s)) 2286 else if (llsl > lsl && strsfx(s, lsuf)) 2287 lsuf[llsl - lsl] = '\0'; 2290 bcs = lsl; 2569 int stl, lpl, lsl, ml; local 2938 lsl = (cm->psuf ? strlen(cm->psuf) : 0); 2939 ml = stl + lpl + lsl; [all...] |
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/ARM/Disassembler/ |
H A D | ARMDisassembler.cpp | 1141 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1144 Shift = ARM_AM::lsl; 1180 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1183 Shift = ARM_AM::lsl; 1508 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1511 Opc = ARM_AM::lsl; 1533 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1553 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1556 ShOp = ARM_AM::lsl;
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/macosx-10.9.5/vim-53/runtime/syntax/ |
H A D | fasm.vim | 62 syn keyword fasmInstr loopnzw loopw loopz loopzd loopzw lsl lss ltr maskmovdqu maskmovq
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H A D | lsl.vim | 270 let b:current_syntax = "lsl"
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H A D | ocaml.vim | 177 syn keyword ocamlOperator asr lor lsl lsr lxor mod not
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 168 return parsePKHImm(O, "lsl", 0, 31); 964 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 || 978 // Only lsl #{0, 1, 2, 3} allowed. 981 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3) 2385 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl") 2510 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0. 2523 .Case("asl", ARM_AM::lsl) 2524 .Case("lsl", ARM_AM::lsl) 2568 // lsl, ro [all...] |
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/ARM/InstPrinter/ |
H A D | ARMInstPrinter.cpp | 43 if (ShOpc == ARM_AM::no_shift || (ShOpc == ARM_AM::lsl && !ShImm)) 353 << getRegisterName(MO2.getReg()) << ", lsl #1]"; 589 O << ", lsl #" << Amt; 598 O << ", lsl #" << Imm; 1027 O << ", lsl #" << ShAmt;
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