Searched refs:TII (Results 1 - 25 of 160) sorted by relevance

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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Mips/
H A DMipsSERegisterInfo.h24 const MipsSEInstrInfo &TII; member in class:llvm::MipsSERegisterInfo
28 const MipsSEInstrInfo &TII);
H A DMipsLongBranch.cpp68 TII(static_cast<const MipsInstrInfo*>(tm.getInstrInfo())),
88 const MipsInstrInfo *TII; member in class:__anon10439::MipsLongBranch
181 MBBInfos[I].Size += TII->GetInstSizeInBytes(&*MI);
220 unsigned NewOpc = TII->GetOppositeBranchOpc(Br->getOpcode());
221 const MCInstrDesc &NewDesc = TII->get(NewOpc);
282 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
284 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)).addReg(Mips::RA)
286 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::BAL_BR)).addMBB(BalTgtMBB);
287 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LUi), Mips::AT).addImm(Hi)
292 BuildMI(*BalTgtMBB, Pos, DL, TII
376 emitGPDisp(MachineFunction &F, const MipsInstrInfo *TII) argument
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H A DMipsSEFrameLowering.cpp36 const MipsSEInstrInfo &TII = local
56 TII.adjustStackPtr(SP, -StackSize, MBB, MBBI);
61 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(AdjustSPLabel);
78 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(CSLabel);
110 BuildMI(MBB, MBBI, dl, TII.get(ADDu), FP).addReg(SP).addReg(ZERO);
115 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(SetFPLabel);
126 const MipsSEInstrInfo &TII = local
143 BuildMI(MBB, I, dl, TII.get(ADDu), SP).addReg(FP).addReg(ZERO);
153 TII.adjustStackPtr(SP, StackSize, MBB, MBBI);
163 const TargetInstrInfo &TII local
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H A DMips16FrameLowering.cpp32 const MipsInstrInfo &TII = local
43 BuildMI(MBB, MBBI, dl, TII.get(Mips::SaveRaF16)).addImm(StackSize);
50 const MipsInstrInfo &TII = local
61 BuildMI(MBB, MBBI, dl, TII.get(Mips::RestoreRaF16)).addImm(StackSize);
H A DMipsSERegisterInfo.cpp44 : MipsRegisterInfo(ST), TII(I) {}
59 const MipsSEInstrInfo *II = static_cast<const MipsSEInstrInfo*>(&TII);
123 unsigned Reg = TII.loadImmediate(Offset, MBB, II, DL, &NewImm);
124 BuildMI(MBB, II, DL, TII.get(ADDu), ATReg).addReg(FrameReg).addReg(Reg);
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Hexagon/
H A DHexagonExpandPredSpillCode.cpp66 const HexagonInstrInfo *TII = QTM.getInstrInfo(); local
87 if (!TII->isValidOffset(Hexagon::STriw_indexed, Offset)) {
88 if (!TII->isValidOffset(Hexagon::ADD_ri, Offset)) {
90 TII->get(Hexagon::CONST32_Int_Real),
92 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::ADD_rr),
95 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_RsPd),
98 TII->get(Hexagon::STriw_indexed))
102 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::ADD_ri),
104 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_RsPd),
107 TII
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H A DHexagonSplitTFRCondSets.cpp74 const TargetInstrInfo *TII = QTM.getInstrInfo(); local
106 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Opc1),
110 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Opc2),
126 TII->get(Hexagon::TFR_cPt), DestReg).
131 TII->get(Hexagon::TFRI_cNotPt), DestReg).
136 TII->get(Hexagon::TFRI_cNotPt_f), DestReg).
152 TII->get(Hexagon::TFRI_cPt), DestReg).
157 TII->get(Hexagon::TFRI_cPt_f), DestReg).
166 TII->get(Hexagon::TFR_cNotPt), DestReg).
182 TII
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H A DHexagonRegisterInfo.cpp44 TII(tii) {
167 TII.isValidOffset(MI.getOpcode(), (FrameSize+Offset)) &&
168 !TII.isSpillPredRegOp(&MI)) {
174 if (!TII.isValidOffset(MI.getOpcode(), Offset)) {
196 if (!TII.isValidOffset(Hexagon::ADD_ri, Offset)) {
198 TII.get(Hexagon::CONST32_Int_Real), dstReg).addImm(Offset);
200 TII.get(Hexagon::ADD_rr),
204 TII.get(Hexagon::ADD_ri),
225 if (!TII.isValidOffset(Hexagon::ADD_ri, Offset)) {
227 TII
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H A DHexagonFrameLowering.cpp145 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); local
149 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::ALLOCFRAME)).addImm(0);
152 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::CONST32_Int_Real),
154 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::SUB_rr),
159 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::ALLOCFRAME)).addImm(NumBytes);
187 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); local
196 BuildMI(MBB, MBBI_end, dl, TII.get(Hexagon::DEALLOC_RET_V4))
199 BuildMI(MBB, MBBI, dl, TII.get(Hexagon::DEALLOCFRAME)).addImm(NumBytes);
229 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo(); local
260 TII
284 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo(); local
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Sparc/
H A DSparcFrameLowering.cpp32 const SparcInstrInfo &TII = local
55 BuildMI(MBB, MBBI, dl, TII.get(SP::SAVEri), SP::O6)
61 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
63 BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1)
65 BuildMI(MBB, MBBI, dl, TII.get(SP::SAVErr), SP::O6)
73 const SparcInstrInfo &TII = local
78 BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
H A DSparcRegisterInfo.h30 const TargetInstrInfo &TII; member in struct:llvm::SparcRegisterInfo
/macosx-10.9.5/llvmCore-3425.0.33/include/llvm/CodeGen/
H A DTargetSchedule.h36 const TargetInstrInfo *TII; member in class:llvm::TargetSchedModel
38 TargetSchedModel(): STI(0), TII(0) {}
49 const TargetInstrInfo *getInstrInfo() const { return TII; }
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/CellSPU/
H A DSPUFrameLowering.cpp95 const SPUInstrInfo &TII = local
120 BuildMI(MBB, MBBI, dl, TII.get(SPU::PROLOG_LABEL)).addSym(FrameLabel);
125 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R0).addImm(16)
129 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R1).addImm(FrameSize)
132 BuildMI(MBB, MBBI, dl, TII.get(SPU::AIr32), SPU::R1).addReg(SPU::R1)
137 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr128), SPU::R2)
140 BuildMI(MBB, MBBI, dl, TII.get(SPU::ILr32), SPU::R2)
142 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQXr32), SPU::R1)
145 BuildMI(MBB, MBBI, dl, TII.get(SPU::Ar32), SPU::R1)
148 BuildMI(MBB, MBBI, dl, TII
191 const SPUInstrInfo &TII = local
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H A DSPUNopFiller.cpp31 const TargetInstrInfo *TII; member in struct:__anon10379::SPUNopFiller
37 : MachineFunctionPass(ID), TM(tm), TII(tm.getInstrInfo()),
96 BuildMI(MBB, I, I->getDebugLoc(), TII->get(SPU::ENOP));
105 BuildMI(MBB, I, I->getDebugLoc(), TII->get(SPU::LNOP));
121 BuildMI(MBB, J, J->getDebugLoc(), TII->get(SPU::ENOP));
126 BuildMI(MBB, J, DebugLoc(), TII->get(SPU::LNOP));
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/XCore/
H A DXCoreFrameLowering.cpp48 const TargetInstrInfo &TII) {
55 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg)
63 const TargetInstrInfo &TII) {
70 BuildMI(MBB, I, dl, TII.get(Opcode))
95 const XCoreInstrInfo &TII = local
105 loadFromStack(MBB, MBBI, XCore::R11, 0, dl, TII);
134 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize);
141 BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(FrameLabel);
155 storeToStack(MBB, MBBI, XCore::LR, LRSpillOffset + FrameSize*4, dl, TII);
160 BuildMI(MBB, MBBI, dl, TII
45 loadFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DstReg, int Offset, DebugLoc dl, const TargetInstrInfo &TII) argument
60 storeToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, int Offset, DebugLoc dl, const TargetInstrInfo &TII) argument
216 const XCoreInstrInfo &TII = local
280 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo(); local
311 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo(); local
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H A DXCoreRegisterInfo.cpp41 : XCoreGenRegisterInfo(XCore::LR), TII(tii) {
139 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode))
144 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode), XCore::SP)
229 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
234 BuildMI(MBB, II, dl, TII.get(XCore::STW_3r))
240 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
250 BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg)
255 BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus))
261 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg)
279 BuildMI(MBB, II, dl, TII
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/PowerPC/
H A DPPCBranchSelector.cpp56 const PPCInstrInfo *TII = local
71 BlockSize += TII->GetInstSizeInBytes(MBBI);
107 MBBStartOffset += TII->GetInstSizeInBytes(I);
152 BuildMI(MBB, I, dl, TII->get(PPC::BCC))
155 BuildMI(MBB, I, dl, TII->get(PPC::BDZ)).addImm(2);
157 BuildMI(MBB, I, dl, TII->get(PPC::BDZ8)).addImm(2);
159 BuildMI(MBB, I, dl, TII->get(PPC::BDNZ)).addImm(2);
161 BuildMI(MBB, I, dl, TII->get(PPC::BDNZ8)).addImm(2);
167 I = BuildMI(MBB, I, dl, TII->get(PPC::B)).addMBB(Dest);
H A DPPCFrameLowering.cpp99 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) { argument
137 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
141 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
146 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
150 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
155 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
159 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
163 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
272 const PPCInstrInfo &TII = local
287 HandleVRSaveUpdate(MBBI, TII);
543 const PPCInstrInfo &TII = local
1019 const PPCInstrInfo &TII = local
1076 const PPCInstrInfo &TII = local
1122 const PPCInstrInfo &TII = local
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/MSP430/
H A DMSP430BranchSelector.cpp55 const MSP430InstrInfo *TII = local
70 BlockSize += TII->GetInstSizeInBytes(MBBI);
107 MBBStartOffset += TII->GetInstSizeInBytes(I);
154 TII->ReverseBranchCondition(Cond);
155 BuildMI(MBB, I, dl, TII->get(MSP430::JCC))
161 I = BuildMI(MBB, I, dl, TII->get(MSP430::Bi)).addMBB(Dest);
H A DMSP430FrameLowering.cpp45 const MSP430InstrInfo &TII = local
66 BuildMI(MBB, MBBI, DL, TII.get(MSP430::PUSH16r))
70 BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::FPW)
98 BuildMI(MBB, MBBI, DL, TII.get(MSP430::SUB16ri), MSP430::SPW)
110 const MSP430InstrInfo &TII = local
135 BuildMI(MBB, MBBI, DL, TII.get(MSP430::POP16r), MSP430::FPW);
157 TII.get(MSP430::MOV16rr), MSP430::SPW).addReg(MSP430::FPW);
161 TII.get(MSP430::SUB16ri), MSP430::SPW)
170 BuildMI(MBB, MBBI, DL, TII.get(MSP430::ADD16ri), MSP430::SPW)
191 const TargetInstrInfo &TII local
217 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); local
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H A DMSP430RegisterInfo.cpp37 : MSP430GenRegisterInfo(MSP430::PCW), TM(tm), TII(tii) {
123 if (Old->getOpcode() == TII.getCallFrameSetupOpcode()) {
125 TII.get(MSP430::SUB16ri), MSP430::SPW)
128 assert(Old->getOpcode() == TII.getCallFrameDestroyOpcode());
134 TII.get(MSP430::ADD16ri), MSP430::SPW)
146 } else if (I->getOpcode() == TII.getCallFrameDestroyOpcode()) {
152 BuildMI(MF, Old->getDebugLoc(), TII.get(MSP430::SUB16ri),
201 MI.setDesc(TII.get(MSP430::MOV16rr));
210 BuildMI(MBB, llvm::next(II), dl, TII.get(MSP430::SUB16ri), DstReg)
213 BuildMI(MBB, llvm::next(II), dl, TII
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/ARM/
H A DThumb1FrameLowering.cpp39 const TargetInstrInfo &TII, DebugLoc dl,
42 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII,
53 const Thumb1InstrInfo &TII = local
73 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -VARegSaveSize,
78 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes,
135 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
146 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes,
167 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), BasePtr)
211 const Thumb1InstrInfo &TII = local
221 emitSPUpdate(MBB, MBBI, TII, d
37 emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const TargetInstrInfo &TII, DebugLoc dl, const Thumb1RegisterInfo &MRI, int NumBytes, unsigned MIFlags = MachineInstr::NoFlags) argument
300 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); local
339 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); local
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H A DARMHazardRecognizer.h31 const ARMBaseInstrInfo &TII; member in class:llvm::ARMHazardRecognizer
44 ScoreboardHazardRecognizer(ItinData, DAG, "post-RA-sched"), TII(tii),
H A DThumb1RegisterInfo.cpp78 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRpci))
95 const TargetInstrInfo &TII,
117 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
120 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
122 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tRSB), LdReg))
131 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
171 int NumBytes, const TargetInstrInfo &TII,
231 TII, MRI, MIFlags);
241 const MCInstrDesc &MCID = TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3);
247 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII
90 emitThumbRegPlusImmInReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, bool CanChangeCC, const TargetInstrInfo &TII, const ARMBaseRegisterInfo& MRI, unsigned MIFlags = MachineInstr::NoFlags) argument
167 emitThumbRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, const TargetInstrInfo &TII, const ARMBaseRegisterInfo& MRI, unsigned MIFlags) argument
299 emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const TargetInstrInfo &TII, DebugLoc dl, const Thumb1RegisterInfo &MRI, int NumBytes) argument
342 emitThumbConstant(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, unsigned DestReg, int Imm, const TargetInstrInfo &TII, const Thumb1RegisterInfo& MRI, DebugLoc dl) argument
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/macosx-10.9.5/llvmCore-3425.0.33/lib/CodeGen/
H A DTargetSchedule.cpp44 TII = tii;
51 return (UOps >= 0) ? UOps : TII->getNumMicroOps(&InstrItins, MI);
78 return TII->defaultDefLatency(&SchedModel, DefMI);
150 TII->getOperandLatency(&InstrItins, DefMI, DefOperIdx, UseMI, UseOperIdx);
160 unsigned InstrLatency = TII->getInstrLatency(&InstrItins, DefMI);
163 // Rather than directly querying InstrItins stage latency, we call a TII
166 // special cases without TII hooks.
169 TII->defaultDefLatency(&SchedModel, DefMI));
211 return TII->getInstrLatency(&InstrItins, MI);
227 return TII
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