Searched refs:ShiftReg (Results 1 - 3 of 3) sorted by relevance
| /macosx-10.9.5/llvmCore-3425.0.33/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 1081 unsigned ShiftReg = RI.createVirtualRegister(RC); local
1097 // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB]
1099 // ShiftReg2 = shift ShiftReg
1101 BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftReg)
1108 .addReg(ShiftReg);
1116 // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB]
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| /macosx-10.9.5/llvmCore-3425.0.33/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 4977 unsigned ShiftReg = RegInfo.createVirtualRegister(RC); local
5022 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
5031 .addReg(incr).addReg(ShiftReg);
5039 .addReg(Mask2Reg).addReg(ShiftReg);
5064 .addReg(ShiftReg);
5325 unsigned ShiftReg = RegInfo.createVirtualRegister(RC); local
5380 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
5389 .addReg(newval).addReg(ShiftReg);
5391 .addReg(oldval).addReg(ShiftReg);
5400 .addReg(Mask2Reg).addReg(ShiftReg);
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| /macosx-10.9.5/llvmCore-3425.0.33/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 389 unsigned ShiftReg; member in struct:__anon10340::ARMOperand::__anon10341::__anon10357
1450 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
2133 unsigned ShiftReg,
2139 Op->RegShiftedReg.ShiftReg = ShiftReg;
2392 << " " << RegShiftedReg.ShiftReg << ">";
2544 int ShiftReg = 0; local
2549 ShiftReg = SrcReg;
2582 ShiftReg = tryParseRegister();
2584 if (ShiftReg
2131 CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg, unsigned ShiftReg, unsigned ShiftImm, SMLoc S, SMLoc E) argument
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