Searched refs:ShiftImm (Results 1 - 3 of 3) sorted by relevance
| /macosx-10.9.5/llvmCore-3425.0.33/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 369 unsigned ShiftImm; // shift for OffsetReg. member in struct:__anon10340::ARMOperand::__anon10341::__anon10354
379 unsigned ShiftImm; member in struct:__anon10340::ARMOperand::__anon10341::__anon10355
390 unsigned ShiftImm; member in struct:__anon10340::ARMOperand::__anon10341::__anon10357
395 unsigned ShiftImm; member in struct:__anon10340::ARMOperand::__anon10341::__anon10358
964 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
981 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1452 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1461 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
1688 Memory.ShiftImm, Memor
2131 CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg, unsigned ShiftReg, unsigned ShiftImm, SMLoc S, SMLoc E) argument
2146 CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, unsigned SrcReg, unsigned ShiftImm, SMLoc S, SMLoc E) argument
2262 CreateMem(unsigned BaseRegNum, const MCConstantExpr *OffsetImm, unsigned OffsetRegNum, ARM_AM::ShiftOpc ShiftType, unsigned ShiftImm, unsigned Alignment, bool isNegative, SMLoc S, SMLoc E) argument
2283 CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy, unsigned ShiftImm, SMLoc S, SMLoc E) argument
3794 unsigned ShiftImm = 0; local
4361 unsigned ShiftImm = 0; local
[all...] |
| /macosx-10.9.5/llvmCore-3425.0.33/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 2649 unsigned ShiftImm; local
2652 ShiftImm = CI->getZExtValue();
2656 if (ShiftImm == 0 || ShiftImm >=32)
2680 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, ShiftImm));
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| /macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 1384 int64_t ShiftImm = (Size == 1) ? 24 : 16; local
1391 .addReg(SrlRes).addImm(ShiftImm);
1393 .addReg(SllRes).addImm(ShiftImm);
1611 int64_t ShiftImm = (Size == 1) ? 24 : 16; local
1616 .addReg(SrlRes).addImm(ShiftImm);
1618 .addReg(SllRes).addImm(ShiftImm);
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