| /macosx-10.9.5/llvmCore-3425.0.33/include/llvm/CodeGen/ |
| H A D | LatencyPriorityQueue.h | 33 // SUnits - The SUnits for the current graph.
34 std::vector<SUnit> *SUnits; member in class:llvm::LatencyPriorityQueue
53 SUnits = &sunits;
54 NumNodesSolelyBlocking.resize(SUnits->size(), 0);
58 NumNodesSolelyBlocking.resize(SUnits->size(), 0);
65 SUnits = 0;
69 assert(NodeNum < (*SUnits).size());
70 return (*SUnits)[NodeNum].getHeight();
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| H A D | ScheduleDAGInstrs.h | 63 std::vector<std::vector<PhysRegSUOper> > SUnits; member in class:llvm::Reg2SUnitsMap
68 // can provide an iterator over SUnits (values) as well.
85 /// If this register is mapped, return its existing SUnits vector.
86 /// Otherwise map the register and return an empty SUnits vector.
89 assert((!New || SUnits[Reg].empty()) && "stale SUnits vector");
91 return SUnits[Reg];
97 SUnits[Reg].clear();
219 /// buildSchedGraph - Build SUnits from the MachineBasicBlock that we are
262 const SUnit *Addr = SUnits
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| H A D | ResourcePriorityQueue.h | 39 /// SUnits - The SUnits for the current graph.
40 std::vector<SUnit> *SUnits; member in class:llvm::ResourcePriorityQueue
89 NumNodesSolelyBlocking.resize(SUnits->size(), 0);
95 SUnits = 0;
99 assert(NodeNum < (*SUnits).size());
100 return (*SUnits)[NodeNum].getHeight();
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| H A D | ScheduleDAG.h | 93 /// classes which require default constructors. SUnits may not
201 /// as "must alias", meaning that the SUnits at either end of the edge
257 // Preds/Succs - The SUnits before/after us in the graph.
471 virtual void initNodes(std::vector<SUnit> &SUnits) = 0;
524 std::vector<SUnit> SUnits; // The scheduling units. member in class:llvm::ScheduleDAG
568 /// VerifyScheduledDAG - Verify that all SUnits were scheduled and that
569 /// their state is consistent. Return the number of scheduled SUnits.
643 return G->SUnits.begin();
646 return G->SUnits.end();
651 /// ordering for SUnits an
658 std::vector<SUnit> &SUnits; member in class:llvm::ScheduleDAGTopologicalSort
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| /macosx-10.9.5/llvmCore-3425.0.33/lib/CodeGen/SelectionDAG/ |
| H A D | ScheduleDAGVLIW.cpp | 52 /// AvailableQueue - The priority queue to use for the available SUnits.
102 AvailableQueue->initNodes(SUnits);
173 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
175 if (SUnits[i].Preds.empty()) {
176 AvailableQueue->push(&SUnits[i]);
177 SUnits[i].isAvailable = true;
184 Sequence.reserve(SUnits.size());
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| H A D | ScheduleDAGSDNodes.cpp | 71 if (!SUnits.empty())
72 Addr = &SUnits[0];
74 SUnits.push_back(SUnit(N, (unsigned)SUnits.size()));
75 assert((Addr == 0 || Addr == &SUnits[0]) &&
76 "SUnits std::vector reallocated on the fly!");
77 SUnits.back().OrigNode = &SUnits.back();
78 SUnit *SU = &SUnits.back();
301 // Cluster loads from "near" addresses into combined SUnits
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| H A D | ScheduleDAGFast.cpp | 64 /// AvailableQueue - The priority queue to use for the available SUnits.
121 DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
122 SUnits[su].dumpAll(this));
268 LoadSU = &SUnits[LoadNode->getNodeId()];
523 if (!SUnits.empty()) {
524 SUnit *RootSU = &SUnits[DAG->getRoot().getNode()->getNodeId()];
534 Sequence.reserve(SUnits.size());
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| H A D | ScheduleDAGRRList.cpp | 116 /// AvailableQueue - The priority queue to use for the available SUnits.
145 /// Topo - A topological ordering for SUnits which permits fast IsReachable
159 Topo(SUnits) {
234 unsigned NumSUnits = SUnits.size();
245 unsigned NumSUnits = SUnits.size();
319 DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
320 SUnits[su].dumpAll(this));
323 AvailableQueue->initNodes(SUnits);
538 SUnit *Def = &SUnits[N->getNodeId()];
968 LoadSU = &SUnits[LoadNod
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| H A D | ResourcePriorityQueue.cpp | 170 SUnits = &sunits;
171 NumNodesSolelyBlocking.resize(SUnits->size(), 0);
173 for (unsigned i = 0, e = SUnits->size(); i != e; ++i) {
174 SUnit *SU = &(*SUnits)[i];
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| H A D | SelectionDAGPrinter.cpp | 296 GW.emitEdge(0, -1, &SUnits[N->getNodeId()], -1,
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| /macosx-10.9.5/llvmCore-3425.0.33/lib/CodeGen/ |
| H A D | ScheduleDAG.cpp | 51 SUnits.clear();
343 /// VerifyScheduledDAG - Verify that all SUnits were scheduled and that
349 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
350 if (!SUnits[i].isScheduled) {
351 if (SUnits[i].NumPreds == 0 && SUnits[i].NumSuccs == 0) {
357 SUnits[i].dump(this);
361 if (SUnits[i].isScheduled &&
362 (isBottomUp ? SUnits[i].getHeight() : SUnits[
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| H A D | AntiDepBreaker.h | 45 virtual unsigned BreakAntiDependencies(const std::vector<SUnit>& SUnits,
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| H A D | CriticalAntiDepBreaker.h | 81 unsigned BreakAntiDependencies(const std::vector<SUnit>& SUnits,
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| H A D | PostRASchedulerList.cpp | 104 /// AvailableQueue - The priority queue to use for the available SUnits.
114 /// Topo - A topological ordering for SUnits.
201 : ScheduleDAGInstrs(MF, MLI, MDT, /*IsPostRA=*/true), Topo(SUnits), AA(AA),
373 AntiDepBreak->BreakAntiDependencies(SUnits, RegionBegin, RegionEnd,
391 DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
392 SUnits[su].dumpAll(this));
394 AvailableQueue.initNodes(SUnits);
654 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
656 bool available = SUnits[i].Preds.empty();
658 AvailableQueue.push(&SUnits[
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| H A D | DFAPacketizer.cpp | 168 for (unsigned i = 0, e = VLIWScheduler->SUnits.size(); i != e; ++i) {
169 SUnit *SU = &VLIWScheduler->SUnits[i];
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| H A D | AggressiveAntiDepBreaker.h | 145 unsigned BreakAntiDependencies(const std::vector<SUnit>& SUnits,
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| H A D | CriticalAntiDepBreaker.cpp | 412 BreakAntiDependencies(const std::vector<SUnit>& SUnits, argument
419 if (SUnits.empty()) return 0;
429 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
430 const SUnit *SU = &SUnits[i];
543 // Also, if there are dependencies on other SUnits with the
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| H A D | AggressiveAntiDepBreaker.cpp | 715 const std::vector<SUnit>& SUnits,
728 if (SUnits.empty()) return 0;
735 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
736 const SUnit *SU = &SUnits[i];
747 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
748 const SUnit *SU = &SUnits[i];
852 // Also, if there are dependencies on other SUnits with the
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| H A D | MachineScheduler.cpp | 470 DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
471 SUnits[su].dumpAll(this));
521 I = SUnits.begin(), E = SUnits.end(); I != E; ++I) {
1238 ILP.resize(DAG->SUnits.size());
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| H A D | ScheduleDAGInstrs.cpp | 151 SUnits.resize(Limit);
157 SUnits[*I].clear();
305 // Either insert a new Reg2SUnits entry with an empty SUnits list, or
306 // retrieve the existing SUnits list for this register's uses.
313 // Either insert a new Reg2SUnits entry with an empty SUnits list, or
314 // retrieve the existing SUnits list for this register's defs.
631 /// After initSUnits, the SUnits vector cannot be resized and the scheduler may
640 SUnits.reserve(BB->size());
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| /macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Hexagon/ |
| H A D | HexagonMachineScheduler.cpp | 28 for (unsigned su = 0, e = SUnits.size(); su != e; ++su) {
30 if (SUnits[su].getInstr()->isCall())
31 LastSequentialCall = &(SUnits[su]);
33 else if (SUnits[su].getInstr()->isCompare() && LastSequentialCall)
34 SUnits[su].addPred(SDep(LastSequentialCall, SDep::Order, 0, /*Reg=*/0,
159 for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
160 if (SUnits[su].getHeight() > maxH)
161 maxH = SUnits[su].getHeight();
164 for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
165 if (SUnits[s
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