Searched refs:SLL (Results 1 - 4 of 4) sorted by relevance

/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Mips/
H A DMipsAnalyzeImmediate.cpp45 AddInstr(SeqLs, Inst(SLL, Shamt));
79 // Replace a ADDiu & SLL pair with a LUi.
82 // SLL 18
86 // Check if the first two instructions are ADDiu and SLL and the shift amount
89 (Seq[1].Opc != SLL) || (Seq[1].ImmOpnd < 16))
132 SLL = Mips::SLL;
137 SLL = Mips::DSLL;
H A DMipsAnalyzeImmediate.h43 /// GetInstSeqLsSLL - Get instrucion sequences which end with a SLL to
50 /// ReplaceADDiuSLLWithLUi - Replace an ADDiu & SLL pair with a LUi.
58 unsigned ADDiu, ORi, SLL, LUi; member in class:llvm::MipsAnalyzeImmediate
H A DMipsISelLowering.cpp1322 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1390 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes)
1565 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1615 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes)
2294 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32); local
2295 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32);
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Mips/MCTargetDesc/
H A DMipsMCCodeEmitter.cpp115 // Unfortunately in MIPS both NOT and SLL will come in with Binary == 0
118 if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) && !Binary)

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