Searched refs:Reg2 (Results 1 - 13 of 13) sorted by relevance

/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/X86/
H A DX86InstrBuilder.h116 unsigned Reg2, bool isKill2) {
118 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0);
114 addRegReg(const MachineInstrBuilder &MIB, unsigned Reg1, bool isKill1, unsigned Reg2, bool isKill2) argument
H A DX86FastISel.cpp1489 unsigned Reg2 = getRegForValue(Op2); local
1491 if (Reg1 == 0 || Reg2 == 0)
1507 .addReg(Reg1).addReg(Reg2);
/macosx-10.9.5/llvmCore-3425.0.33/lib/CodeGen/
H A DAggressiveAntiDepBreaker.h101 // UnionGroups - Union Reg1's and Reg2's groups to form a new
104 unsigned UnionGroups(unsigned Reg1, unsigned Reg2);
H A DTargetInstrInfoImpl.cpp80 unsigned Reg2 = MI->getOperand(Idx2).getReg(); local
91 Reg0 = Reg2;
93 } else if (HasDef && Reg0 == Reg2 &&
111 MI->getOperand(Idx1).setReg(Reg2);
H A DAggressiveAntiDepBreaker.cpp80 unsigned AggressiveAntiDepState::UnionGroups(unsigned Reg1, unsigned Reg2) argument
87 unsigned Group2 = GetGroup(Reg2);
H A DStrongPHIElimination.cpp438 void StrongPHIElimination::unionRegs(unsigned Reg1, unsigned Reg2) { argument
440 Node *Node2 = RegNodeMap[Reg2]->getLeader();
/macosx-10.9.5/llvmCore-3425.0.33/include/llvm/MC/
H A DMCRegisterInfo.h76 bool contains(unsigned Reg1, unsigned Reg2) const {
77 return contains(Reg1) && contains(Reg2);
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/ARM/
H A DThumb2SizeReduction.cpp603 unsigned Reg2 = MI->getOperand(2).getReg(); local
606 || !isARMLowRegister(Reg2))
608 if (Reg0 != Reg2) {
636 unsigned Reg2 = MI->getOperand(2).getReg(); local
637 if (Entry.LowRegs2 && !isARMLowRegister(Reg2))
H A DARMFastISel.cpp2666 unsigned Reg2 = 0; local
2668 Reg2 = getRegForValue(Src2Value);
2669 if (Reg2 == 0) return false;
2682 MIB.addReg(Reg2);
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp160 unsigned Reg2 = MI->getOperand(2).getReg(); local
180 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
184 .addReg(Reg2, getKillRegState(Reg2IsKill))
191 MI->getOperand(0).setReg(Reg2);
193 MI->getOperand(1).setReg(Reg2);
/macosx-10.9.5/llvmCore-3425.0.33/include/llvm/Target/
H A DTargetRegisterInfo.h80 bool contains(unsigned Reg1, unsigned Reg2) const {
81 return MC->contains(Reg1, Reg2);
/macosx-10.9.5/llvmCore-3425.0.33/utils/TableGen/
H A DCodeGenRegisters.cpp1154 CodeGenRegister *Reg2 = i1->second; local
1156 if (Reg1 == Reg2)
1158 const CodeGenRegister::SubRegMap &SRM2 = Reg2->getSubRegs();
1165 if (Reg2 == Reg3)
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Mips/
H A DMipsISelLowering.cpp2589 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize); local
2590 if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
3343 unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(), local
3345 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT);

Completed in 408 milliseconds