/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Mips/ |
H A D | MipsSEInstrInfo.cpp | 44 unsigned Opc = MI->getOpcode(); local 46 if ((Opc == Mips::LW) || (Opc == Mips::LW_P8) || (Opc == Mips::LD) || 47 (Opc == Mips::LD_P8) || (Opc == Mips::LWC1) || (Opc == Mips::LWC1_P8) || 48 (Opc == Mips::LDC1) || (Opc == Mips::LDC164) || 49 (Opc 69 unsigned Opc = MI->getOpcode(); local 89 unsigned Opc = 0, ZeroReg = 0; local 163 unsigned Opc = 0; local 190 unsigned Opc = 0; local [all...] |
H A D | Mips16InstrInfo.cpp | 61 unsigned Opc = 0, ZeroReg = 0; local 65 Opc = Mips::Move32R16; 68 assert(Opc && "Cannot copy registers"); 70 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc)); 90 unsigned Opc = 0; local 92 Opc = Mips::SwRxSpImmX16; 93 assert(Opc && "Register class not handled!"); 94 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)) 106 unsigned Opc = 0; local 109 Opc [all...] |
H A D | MipsAnalyzeImmediate.h | 20 unsigned Opc, ImmOpnd; member in struct:llvm::MipsAnalyzeImmediate::Inst 21 Inst(unsigned Opc, unsigned ImmOpnd);
|
H A D | Mips16InstrInfo.h | 65 virtual unsigned GetOppositeBranchOpc(unsigned Opc) const; 68 virtual unsigned GetAnalyzableBrOpc(unsigned Opc) const; 71 unsigned Opc) const;
|
H A D | MipsInstrInfo.h | 69 virtual unsigned GetOppositeBranchOpc(unsigned Opc) const = 0; 81 virtual unsigned GetAnalyzableBrOpc(unsigned Opc) const = 0; 83 void AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
|
H A D | MipsSEInstrInfo.h | 66 virtual unsigned GetOppositeBranchOpc(unsigned Opc) const; 80 virtual unsigned GetAnalyzableBrOpc(unsigned Opc) const; 83 unsigned Opc) const;
|
H A D | MipsAnalyzeImmediate.cpp | 15 MipsAnalyzeImmediate::Inst::Inst(unsigned O, unsigned I) : Opc(O), ImmOpnd(I) {} 88 if ((Seq.size() < 2) || (Seq[0].Opc != ADDiu) || 89 (Seq[1].Opc != SLL) || (Seq[1].ImmOpnd < 16)) 100 Seq[0].Opc = LUi;
|
H A D | MipsISelDAGToDAG.cpp | 89 std::pair<SDNode*, SDNode*> SelectMULT(SDNode *N, unsigned Opc, DebugLoc dl, 367 MipsDAGToDAGISel::SelectMULT(SDNode *N, unsigned Opc, DebugLoc dl, EVT Ty, argument 370 SDNode *Mul = CurDAG->getMachineNode(Opc, dl, MVT::Glue, N->getOperand(0), 415 unsigned Opc = InFlag.getOpcode(); (void)Opc; local 416 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) || 417 (Opc == ISD::SUBC || Opc == ISD::SUBE)) && 524 if (Inst->Opc [all...] |
H A D | MipsInstrInfo.cpp | 77 void MipsInstrInfo::AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc, argument 80 assert(GetAnalyzableBrOpc(Opc) && "Not an analyzable branch"); 86 Cond.push_back(MachineOperand::CreateImm(Opc)); 177 unsigned Opc = Cond[0].getImm(); local 178 const MCInstrDesc &MCID = get(Opc);
|
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/ARM/ |
H A D | ARMInstrInfo.h | 33 // Return the non-pre/post incrementing version of 'Opc'. Return 0 35 unsigned getUnindexedOpcode(unsigned Opc) const;
|
H A D | ARMBaseInstrInfo.h | 41 // Return the non-pre/post incrementing version of 'Opc'. Return 0 43 virtual unsigned getUnindexedOpcode(unsigned Opc) const =0; 341 bool isUncondBranchOpcode(int Opc) { argument 342 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B; 346 bool isCondBranchOpcode(int Opc) { argument 347 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc 351 isJumpTableBranchOpcode(int Opc) argument 357 isIndirectBranchOpcode(int Opc) argument [all...] |
H A D | ARMInstrInfo.cpp | 52 unsigned ARMInstrInfo::getUnindexedOpcode(unsigned Opc) const { 53 switch (Opc) { 122 unsigned Opc = TM->getSubtarget<ARMSubtarget>().isThumb2() ? local 126 TII.get(Opc), GlobalBaseReg) 128 if (Opc == ARM::LDRcp)
|
H A D | Thumb1InstrInfo.h | 32 // Return the non-pre/post incrementing version of 'Opc'. Return 0 34 unsigned getUnindexedOpcode(unsigned Opc) const;
|
H A D | Thumb2InstrInfo.h | 33 // Return the non-pre/post incrementing version of 'Opc'. Return 0 35 unsigned getUnindexedOpcode(unsigned Opc) const;
|
H A D | ARMISelDAGToDAG.cpp | 110 bool SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc); 113 SDValue &Offset, SDValue &Opc); 115 SDValue &Opc) { 116 return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_BASE; 120 SDValue &Opc) { 121 return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_SHOP; 125 SDValue &Opc) { 126 SelectAddrMode2Worker(N, Base, Offset, Opc); 127 // return SelectAddrMode2ShOp(N, Base, Offset, Opc); 133 SDValue &Offset, SDValue &Opc); 114 SelectAddrMode2Base(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc) argument 119 SelectAddrMode2ShOp(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc) argument 124 SelectAddrMode2(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc) argument 302 isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) argument 387 SelectImmShifterOperand(SDValue N, SDValue &BaseReg, SDValue &Opc, bool CheckProfitability) argument 410 SelectRegShifterOperand(SDValue N, SDValue &BaseReg, SDValue &ShReg, SDValue &Opc, bool CheckProfitability) argument 488 SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc) argument 585 SelectAddrMode2Worker(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc) argument 721 SelectAddrMode2OffsetReg(SDNode *Op, SDValue N, SDValue &Offset, SDValue &Opc) argument 757 SelectAddrMode2OffsetImmPre(SDNode *Op, SDValue N, SDValue &Offset, SDValue &Opc) argument 777 SelectAddrMode2OffsetImm(SDNode *Op, SDValue N, SDValue &Offset, SDValue &Opc) argument 802 SelectAddrMode3(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc) argument 850 SelectAddrMode3Offset(SDNode *Op, SDValue N, SDValue &Offset, SDValue &Opc) argument 1151 SelectT2ShifterOperandReg(SDValue N, SDValue &BaseReg, SDValue &Opc) argument 1551 getVLDSTRegisterUpdateOpcode(unsigned Opc) argument 1653 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] : local 1804 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] : local 1972 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] : local 2037 unsigned Opc = Opcodes[OpcodeIndex]; local 2078 SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, unsigned Opc) argument 2116 unsigned Opc = isSigned ? (Subtarget->isThumb() ? ARM::t2SBFX : ARM::SBFX) local 2179 unsigned Opc = 0; local 2224 unsigned Opc = 0; local 2255 unsigned Opc = 0; local 2351 unsigned Opc = 0; local 2417 SelectAtomic64(SDNode *Node, unsigned Opc) argument 2510 unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ? local 2579 unsigned Opc = (Subtarget->isThumb() && Subtarget->hasThumb2()) local 2700 unsigned Opc = Subtarget->isThumb() ? local 2729 unsigned Opc = 0; local 2749 unsigned Opc = 0; local 2769 unsigned Opc = 0; local [all...] |
H A D | Thumb1RegisterInfo.cpp | 129 int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr); local 131 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg); 132 if (Opc != ARM::tADDhirr) 143 static unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes, argument 148 if (Opc == ARM::tADDrSPi) { 182 int Opc = 0; 190 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi; 203 Opc = ARM::tADDrSPi; 212 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi; 217 Opc 328 unsigned Opc = Old->getOpcode(); local [all...] |
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Hexagon/ |
H A D | HexagonCFGOptimizer.cpp | 53 static bool IsConditionalBranch(int Opc) { argument 54 return (Opc == Hexagon::JMP_c) || (Opc == Hexagon::JMP_cNot) 55 || (Opc == Hexagon::JMP_cdnPt) || (Opc == Hexagon::JMP_cdnNotPt); 59 static bool IsUnconditionalJump(int Opc) { argument 60 return (Opc == Hexagon::JMP); 106 int Opc = MI->getOpcode(); local 107 if (IsConditionalBranch(Opc)) {
|
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/X86/ |
H A D | X86FrameLowering.cpp | 107 unsigned Opc = MBBI->getOpcode(); local 108 switch (Opc) { 152 unsigned Opc; 154 Opc = getLEArOpcode(Is64Bit); 156 Opc = isSub 171 Opc = isSub 174 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc)) 186 MI = addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr), 189 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr) 209 unsigned Opc [all...] |
H A D | X86FastISel.cpp | 88 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT, 181 unsigned Opc = 0; local 187 Opc = X86::MOV8rm; 191 Opc = X86::MOV16rm; 195 Opc = X86::MOV32rm; 200 Opc = X86::MOV64rm; 205 Opc = Subtarget->hasAVX() ? X86::VMOVSSrm : X86::MOVSSrm; 208 Opc = X86::LD_Fp32m; 214 Opc = Subtarget->hasAVX() ? X86::VMOVSDrm : X86::MOVSDrm; 217 Opc 239 unsigned Opc = 0; local 290 unsigned Opc = 0; local 324 X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT, unsigned &ResultReg) argument 540 unsigned Opc = 0; local 1238 unsigned Opc = 0; local 1509 unsigned Opc = X86::SETBr; local 1957 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64; local 2038 unsigned Opc = 0; local 2146 unsigned Opc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r; local 2160 unsigned Opc = 0; local [all...] |
H A D | X86ISelDAGToDAG.cpp | 192 SDNode *SelectGather(SDNode *N, unsigned Opc); 193 SDNode *SelectAtomic64(SDNode *Node, unsigned Opc); 1486 SDNode *X86DAGToDAGISel::SelectAtomic64(SDNode *Node, unsigned Opc) { argument 1498 SDNode *ResNode = CurDAG->getMachineNode(Opc, Node->getDebugLoc(), 1721 unsigned Opc = 0; local 1726 Opc = AtomicOpcTbl[Op][ConstantI8]; 1728 Opc = AtomicOpcTbl[Op][I8]; 1733 Opc = AtomicOpcTbl[Op][SextConstantI16]; 1735 Opc = AtomicOpcTbl[Op][ConstantI16]; 1737 Opc 1845 isLoadIncOrDecStore(StoreSDNode *StoreNode, unsigned Opc, SDValue StoredVal, SelectionDAG *CurDAG, LoadSDNode* &LoadNode, SDValue &InputChain) argument 1930 getFusedLdStOpcode(EVT &LdVT, unsigned Opc) argument 1948 SelectGather(SDNode *Node, unsigned Opc) argument 1980 unsigned Opc, MOpc; local 2013 unsigned Opc; local 2057 unsigned Opc; local 2649 unsigned Opc = StoredVal->getOpcode(); local 2702 unsigned Opc = Subtarget->hasAVX() ? X86::VPCMPESTRIrr : local 2738 unsigned Opc = Subtarget->hasAVX() ? X86::VPCMPISTRIrr : local [all...] |
/macosx-10.9.5/llvmCore-3425.0.33/include/llvm/ |
H A D | InstrTypes.h | 196 static BinaryOperator *CreateNSW(BinaryOps Opc, Value *V1, Value *V2, argument 198 BinaryOperator *BO = Create(Opc, V1, V2, Name); 202 static BinaryOperator *CreateNSW(BinaryOps Opc, Value *V1, Value *V2, argument 204 BinaryOperator *BO = Create(Opc, V1, V2, Name, BB); 208 static BinaryOperator *CreateNSW(BinaryOps Opc, Value *V1, Value *V2, argument 210 BinaryOperator *BO = Create(Opc, V1, V2, Name, I); 215 static BinaryOperator *CreateNUW(BinaryOps Opc, Value *V1, Value *V2, argument 217 BinaryOperator *BO = Create(Opc, V1, V2, Name); 221 static BinaryOperator *CreateNUW(BinaryOps Opc, Value *V1, Value *V2, argument 223 BinaryOperator *BO = Create(Opc, V 227 CreateNUW(BinaryOps Opc, Value *V1, Value *V2, const Twine &Name, Instruction *I) argument 234 CreateExact(BinaryOps Opc, Value *V1, Value *V2, const Twine &Name = �) argument 240 CreateExact(BinaryOps Opc, Value *V1, Value *V2, const Twine &Name, BasicBlock *BB) argument 246 CreateExact(BinaryOps Opc, Value *V1, Value *V2, const Twine &Name, Instruction *I) argument [all...] |
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/MBlaze/ |
H A D | MBlazeInstrInfo.h | 144 inline static bool isUncondBranchOpcode(int Opc) { argument 145 switch (Opc) { 155 inline static bool isCondBranchOpcode(int Opc) { argument 156 switch (Opc) {
|
H A D | MBlazeISelDAGToDAG.cpp | 101 unsigned Opc = N->getOpcode(); local 102 if (Opc != ISD::Constant) 213 unsigned Opc = MBlaze::ADDIK; local 215 return CurDAG->SelectNodeTo(Node, Opc, VT, TFI, imm); 216 return CurDAG->getMachineNode(Opc, dl, VT, TFI, imm);
|
/macosx-10.9.5/llvmCore-3425.0.33/utils/TableGen/ |
H A D | FixedLenDecoderEmitter.cpp | 421 void SingletonExists(unsigned Opc) const; 439 unsigned Opc) const; 441 bool doesOpcodeNeedPredicate(unsigned Opc) const; 444 unsigned Opc) const; 447 unsigned Opc) const; 451 unsigned Opc) const; 460 void emitDecoder(raw_ostream &OS, unsigned Indentation, unsigned Opc) const; 461 unsigned getDecoderIndex(DecoderSet &Decoders, unsigned Opc) const; 819 unsigned Opc = decodeULEB128(Buffer); 831 << NumberedInstructions->at(Opc) [all...] |
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/CellSPU/ |
H A D | SPUISelDAGToDAG.cpp | 401 unsigned Opc = N.getOpcode(); local 404 if (Opc == ISD::FrameIndex) { 415 } else if (Opc == ISD::ADD) { 468 } else if (Opc == SPUISD::IndirectAddr) { 499 } else if (Opc == SPUISD::AFormAddr) { 503 } else if (Opc == SPUISD::LDRESULT) { 507 } else if (Opc == ISD::Register 508 ||Opc == ISD::CopyFromReg 509 ||Opc == ISD::UNDEF 510 ||Opc 606 unsigned Opc = N->getOpcode(); local 762 unsigned Opc = SPU::ROTMAIr32_i32; local 793 unsigned Opc = SPU::DFNMSf64; local 806 unsigned Opc = SPU::XORfneg64; local [all...] |