Searched refs:OL (Results 1 - 25 of 57) sorted by relevance

123

/macosx-10.9.5/llvmCore-3425.0.33/lib/MC/
H A DMCCodeGenInfo.cpp19 CodeGenOpt::Level OL) {
22 OptLevel = OL;
18 InitMCCodeGenInfo(Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Sparc/
H A DSparcTargetMachine.cpp32 CodeGenOpt::Level OL,
34 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
84 CodeGenOpt::Level OL)
85 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
96 CodeGenOpt::Level OL)
97 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
28 SparcTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64bit) argument
78 SparcV8TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
90 SparcV9TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
H A DSparcTargetMachine.h39 CodeGenOpt::Level OL, bool is64bit);
70 CodeGenOpt::Level OL);
82 CodeGenOpt::Level OL);
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Mips/
H A DMipsTargetMachine.cpp42 CodeGenOpt::Level OL,
44 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
65 CodeGenOpt::Level OL)
66 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
74 CodeGenOpt::Level OL)
75 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
39 MipsTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle) argument
62 MipsebTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
71 MipselTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
H A DMipsTargetMachine.h46 CodeGenOpt::Level OL,
91 CodeGenOpt::Level OL);
102 CodeGenOpt::Level OL);
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/NVPTX/
H A DNVPTXTargetMachine.cpp70 CodeGenOpt::Level OL,
72 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
87 CodeGenOpt::Level OL)
88 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
97 CodeGenOpt::Level OL)
98 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
63 NVPTXTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions& Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64bit) argument
83 NVPTXTargetMachine32(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
93 NVPTXTargetMachine64(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/PowerPC/
H A DPPCTargetMachine.cpp39 CodeGenOpt::Level OL,
41 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
59 CodeGenOpt::Level OL)
60 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
69 CodeGenOpt::Level OL)
70 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
35 PPCTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64Bit) argument
55 PPC32TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
65 PPC64TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
H A DPPCTargetMachine.h44 CodeGenOpt::Level OL, bool is64Bit);
81 CodeGenOpt::Level OL);
92 CodeGenOpt::Level OL);
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/MSP430/
H A DMSP430TargetMachine.cpp33 CodeGenOpt::Level OL)
34 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
27 MSP430TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/XCore/
H A DXCoreTargetMachine.cpp27 CodeGenOpt::Level OL)
28 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
23 XCoreTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/ARM/
H A DARMTargetMachine.cpp44 CodeGenOpt::Level OL)
45 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
60 CodeGenOpt::Level OL)
61 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
86 CodeGenOpt::Level OL)
87 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
40 ARMBaseTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
56 ARMTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
82 ThumbTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
H A DARMTargetMachine.h46 CodeGenOpt::Level OL);
75 CodeGenOpt::Level OL);
118 CodeGenOpt::Level OL);
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/
H A DTargetMachineC.cpp101 CodeGenOpt::Level OL; local
105 OL = CodeGenOpt::None;
108 OL = CodeGenOpt::Less;
111 OL = CodeGenOpt::Aggressive;
114 OL = CodeGenOpt::Default;
120 CM, OL));
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/X86/
H A DX86TargetMachine.cpp37 CodeGenOpt::Level OL)
38 : X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false),
60 CodeGenOpt::Level OL)
61 : X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true),
76 CodeGenOpt::Level OL,
78 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
33 X86_32TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
56 X86_64TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
72 X86TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64Bit) argument
H A DX86TargetMachine.h43 CodeGenOpt::Level OL,
92 CodeGenOpt::Level OL);
121 CodeGenOpt::Level OL);
/macosx-10.9.5/llvmCore-3425.0.33/include/llvm/MC/
H A DMCCodeGenInfo.h38 CodeGenOpt::Level OL = CodeGenOpt::Default);
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/CppBackend/
H A DCPPTargetMachine.h28 CodeGenOpt::Level OL)
25 CPPTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/CellSPU/MCTargetDesc/
H A DSPUMCTargetDesc.cpp67 CodeGenOpt::Level OL) {
71 X->InitMCCodeGenInfo(Reloc::Static, CM, OL);
65 createSPUMCCodeGenInfo(StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/CellSPU/
H A DSPUTargetMachine.cpp38 CodeGenOpt::Level OL)
39 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
34 SPUTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCTargetDesc.cpp68 CodeGenOpt::Level OL) {
72 X->InitMCCodeGenInfo(Reloc::Static, CM, OL);
66 createHexagonMCCodeGenInfo(StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/MBlaze/
H A DMBlazeTargetMachine.cpp38 CodeGenOpt::Level OL)
39 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
35 MBlazeTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/MSP430/MCTargetDesc/
H A DMSP430MCTargetDesc.cpp55 CodeGenOpt::Level OL) {
57 X->InitMCCodeGenInfo(RM, CM, OL);
53 createMSP430MCCodeGenInfo(StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/NVPTX/MCTargetDesc/
H A DNVPTXMCTargetDesc.cpp56 CodeGenOpt::Level OL) {
58 X->InitMCCodeGenInfo(RM, CM, OL);
54 createNVPTXMCCodeGenInfo(StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Sparc/MCTargetDesc/
H A DSparcMCTargetDesc.cpp55 CodeGenOpt::Level OL) {
57 X->InitMCCodeGenInfo(RM, CM, OL);
53 createSparcMCCodeGenInfo(StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/XCore/MCTargetDesc/
H A DXCoreMCTargetDesc.cpp66 CodeGenOpt::Level OL) {
68 X->InitMCCodeGenInfo(RM, CM, OL);
64 createXCoreMCCodeGenInfo(StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument

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