/macosx-10.9.5/llvmCore-3425.0.33/lib/CodeGen/ |
H A D | TargetSchedule.cpp | 63 int TargetSchedModel::getDefLatency(const MachineInstr *DefMI, argument 78 return TII->defaultDefLatency(&SchedModel, DefMI); 138 const MachineInstr *DefMI, unsigned DefOperIdx, 142 int DefLatency = getDefLatency(DefMI, FindMin); 150 TII->getOperandLatency(&InstrItins, DefMI, DefOperIdx, UseMI, UseOperIdx); 153 unsigned DefClass = DefMI->getDesc().getSchedClass(); 160 unsigned InstrLatency = TII->getInstrLatency(&InstrItins, DefMI); 169 TII->defaultDefLatency(&SchedModel, DefMI)); 174 const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI); 175 unsigned DefIdx = findDefIdx(DefMI, DefOperId 137 computeOperandLatency( const MachineInstr *DefMI, unsigned DefOperIdx, const MachineInstr *UseMI, unsigned UseOperIdx, bool FindMin) const argument 200 << *DefMI; local 231 computeOutputLatency(const MachineInstr *DefMI, unsigned DefOperIdx, const MachineInstr *DepMI) const argument [all...] |
H A D | LiveRangeEdit.cpp | 46 const MachineInstr *DefMI, 48 assert(DefMI && "Missing instruction"); 50 if (!TII.isTriviallyReMaterializable(DefMI, aa)) 62 MachineInstr *DefMI = LIS.getInstructionFromIndex(VNI->def); local 63 if (!DefMI) 65 checkRematerializable(VNI, DefMI, aa); 162 MachineInstr *DefMI = 0, *UseMI = 0; local 170 if (DefMI && DefMI != MI) 174 DefMI 45 checkRematerializable(VNInfo *VNI, const MachineInstr *DefMI, AliasAnalysis *aa) argument [all...] |
H A D | TargetInstrInfoImpl.cpp | 565 const MachineInstr *DefMI) const { 566 if (DefMI->isTransient()) 568 if (DefMI->mayLoad()) 570 if (isHighLatencyDef(DefMI->getOpcode())) 588 const MachineInstr *DefMI, 593 unsigned DefClass = DefMI->getDesc().getSchedClass(); 598 /// Both DefMI and UseMI must be valid. By default, call directly to the 602 const MachineInstr *DefMI, unsigned DefIdx, 604 unsigned DefClass = DefMI->getDesc().getSchedClass(); 613 const MachineInstr *DefMI, boo 587 hasLowDefLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx) const argument 601 getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument 611 computeDefOperandLatency( const InstrItineraryData *ItinData, const MachineInstr *DefMI, bool FindMin) const argument 652 computeOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx, bool FindMin) const argument [all...] |
H A D | PeepholeOptimizer.cpp | 332 MachineInstr *DefMI = MRI->getVRegDef(Src); local 333 if (!DefMI || !DefMI->isBitcast()) 337 NumDefs = DefMI->getDesc().getNumDefs(); 338 NumSrcs = DefMI->getDesc().getNumOperands() - NumDefs; 342 const MachineOperand &MO = DefMI->getOperand(i); 545 MachineInstr *DefMI = 0; local 547 FoldAsLoadDefReg, DefMI); 549 // Update LocalMIs since we replaced MI with FoldMI and deleted DefMI. 551 LocalMIs.erase(DefMI); [all...] |
H A D | MachineTraceMetrics.cpp | 524 const MachineInstr *DefMI; 528 DataDep(const MachineInstr *DefMI, unsigned DefOp, unsigned UseOp) 529 : DefMI(DefMI), DefOp(DefOp), UseOp(UseOp) {} 537 DefMI = &*DefI; 677 const MachineInstr *DefMI = MTM.MRI->getVRegDef(LIR.Reg); 679 const TraceBlockInfo &DefTBI = BlockInfo[DefMI->getParent()->getNumber()]; 682 unsigned Len = LIR.Height + Cycles[DefMI].Depth; 741 BlockInfo[Dep.DefMI->getParent()->getNumber()]; 746 unsigned DepCycle = Cycles.lookup(Dep.DefMI) [all...] |
H A D | InlineSpiller.cpp | 108 MachineInstr *DefMI; member in struct:__anon10146::InlineSpiller::SibValueInfo 119 SpillReg(Reg), SpillVNI(VNI), SpillMBB(0), DefMI(0) {} 122 bool hasDef() const { return DefByOrigPHI || DefMI; } 329 if (SVI.DefMI) 330 OS << " def: " << *SVI.DefMI; 393 DepSV.DefMI = SV.DefMI; 482 return SVI->second.DefMI; 600 SVI->second.DefMI = MI; 621 return SVI->second.DefMI; 644 MachineInstr *DefMI = 0; local 719 MachineInstr *DefMI = LIS.getInstructionFromIndex(SVI.SpillVNI->def); local [all...] |
H A D | PHIElimination.cpp | 138 MachineInstr *DefMI = *I; local 139 unsigned DefReg = DefMI->getOperand(0).getReg(); 141 DefMI->eraseFromParent(); 327 if (MachineInstr *DefMI = MRI->getVRegDef(SrcReg)) 328 if (DefMI->isImplicitDef()) 329 ImpDefs.insert(DefMI);
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H A D | RegisterCoalescer.cpp | 573 MachineInstr *DefMI = LIS->getInstructionFromIndex(AValNo->def); 574 if (!DefMI) 576 if (!DefMI->isCommutable()) 578 // If DefMI is a two-address instruction then commuting it will change the 580 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg); 583 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx)) 586 if (!TII->findCommutedOpIndices(DefMI, Op1, Op2)) 595 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx); 621 << *DefMI); 625 MachineBasicBlock *MBB = DefMI 1327 computeWriteLanes(const MachineInstr *DefMI, bool &Redef) argument 1375 const MachineInstr *DefMI = 0; local [all...] |
H A D | MachineCSE.cpp | 129 MachineInstr *DefMI = MRI->getVRegDef(Reg); local 130 if (DefMI->getParent() != MBB) 132 if (!DefMI->isCopy()) 134 unsigned SrcReg = DefMI->getOperand(1).getReg(); 137 if (DefMI->getOperand(0).getSubReg() || DefMI->getOperand(1).getSubReg()) 141 DEBUG(dbgs() << "Coalescing: " << *DefMI); 145 DefMI->eraseFromParent();
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H A D | TwoAddressInstructionPass.cpp | 369 MachineInstr *DefMI = &MI; local 371 if (!DefMI->killsRegister(Reg)) 380 DefMI = &*Begin; 385 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) 860 MachineInstr *DefMI = &*DI; local 861 if (DefMI->getParent() != MBB || DefMI->isCopy() || DefMI->isCopyLike()) 863 if (DefMI == MI) 865 DenseMap<MachineInstr*, unsigned>::iterator DDI = DistanceMap.find(DefMI); 1686 MachineInstr *DefMI = NULL; local [all...] |
H A D | EarlyIfConversion.cpp | 244 MachineInstr *DefMI = MRI->getVRegDef(Reg); local 245 if (!DefMI || DefMI->getParent() != Head) 247 if (InsertAfter.insert(DefMI)) 248 DEBUG(dbgs() << "BB#" << MBB->getNumber() << " depends on " << *DefMI); 249 if (DefMI->isTerminator()) {
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H A D | MachineTraceMetrics.h | 282 void addLiveIns(const MachineInstr *DefMI, unsigned DefOp,
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H A D | MachineSink.cpp | 141 MachineInstr *DefMI = MRI->getVRegDef(SrcReg); 142 if (DefMI->isCopyLike()) 144 DEBUG(dbgs() << "Coalescing: " << *DefMI);
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H A D | StrongPHIElimination.cpp | 253 MachineInstr *DefMI = MRI->getVRegDef(SrcReg); local 254 if (DefMI) 255 PHISrcDefs[DefMI->getParent()].push_back(DefMI);
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H A D | TailDuplication.cpp | 236 MachineInstr *DefMI = MRI->getVRegDef(VReg); local 238 if (DefMI) { 239 DefBB = DefMI->getParent();
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H A D | LiveIntervalAnalysis.cpp | 191 MachineInstr *DefMI = getInstructionFromIndex(OldLR->valno->def); local 192 if (DefMI != 0) { 193 return DefMI->findRegisterDefOperandIdx(interval.reg) != -1;
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/macosx-10.9.5/llvmCore-3425.0.33/include/llvm/CodeGen/ |
H A D | TargetSchedule.h | 90 unsigned computeOperandLatency(const MachineInstr *DefMI, unsigned DefOperIdx, 105 unsigned computeOutputLatency(const MachineInstr *DefMI, unsigned DefIdx, 113 int getDefLatency(const MachineInstr *DefMI, bool FindMin) const;
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H A D | LiveRangeEdit.h | 148 /// values if DefMI may be rematerializable. 149 bool checkRematerializable(VNInfo *VNI, const MachineInstr *DefMI,
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/ARM/ |
H A D | ARMHazardRecognizer.cpp | 19 static bool hasRAWHazard(MachineInstr *DefMI, MachineInstr *MI, argument 30 return MI->readsRegister(DefMI->getOperand(0).getReg(), &TRI); 45 MachineInstr *DefMI = LastMI; local 55 DefMI = &*I; 59 if (TII.isFpMLxInstruction(DefMI->getOpcode()) && 61 hasRAWHazard(DefMI, MI, TRI))) {
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H A D | MLxExpansionPass.cpp | 94 MachineInstr *DefMI = MRI->getVRegDef(Reg); local 96 if (DefMI->getParent() != MBB) 98 if (DefMI->isCopyLike()) { 99 Reg = DefMI->getOperand(1).getReg(); 101 DefMI = MRI->getVRegDef(Reg); 104 } else if (DefMI->isInsertSubreg()) { 105 Reg = DefMI->getOperand(2).getReg(); 107 DefMI = MRI->getVRegDef(Reg); 113 return DefMI; 148 MachineInstr *DefMI local [all...] |
H A D | ARMBaseInstrInfo.h | 217 virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, 225 const MachineInstr *DefMI, unsigned DefIdx, 278 const MachineInstr *DefMI, unsigned DefIdx, 281 const MachineInstr *DefMI, unsigned DefIdx) const;
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H A D | ARMBaseInstrInfo.cpp | 1658 MachineInstr *DefMI = canFoldIntoMOVCC(MI->getOperand(2).getReg(), MRI, this); local 1659 bool Invert = !DefMI; 1660 if (!DefMI) 1661 DefMI = canFoldIntoMOVCC(MI->getOperand(1).getReg(), MRI, this); 1662 if (!DefMI) 1665 // Create a new predicated version of DefMI. 1668 DefMI->getDesc(), 1671 // Copy all the DefMI operands, excluding its (null) predicate. 1672 const MCInstrDesc &DefDesc = DefMI->getDesc(); 1675 NewMI.addOperand(DefMI 2241 FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, unsigned Reg, MachineRegisterInfo *MRI) const argument 3069 adjustDefLatency(const ARMSubtarget &Subtarget, const MachineInstr *DefMI, const MCInstrDesc *DefMCID, unsigned DefAlign) argument 3250 getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument 3622 hasHighOperandLatency(const InstrItineraryData *ItinData, const MachineRegisterInfo *MRI, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument 3645 hasLowDefLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx) const argument [all...] |
/macosx-10.9.5/llvmCore-3425.0.33/include/llvm/Target/ |
H A D | TargetInstrInfo.h | 746 /// defined by the load we are trying to fold. DefMI returns the machine 752 MachineInstr *&DefMI) const { 758 virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, argument 791 const MachineInstr *DefMI, unsigned DefIdx, 800 const MachineInstr *DefMI, unsigned DefIdx, 816 const MachineInstr *DefMI) const; 819 const MachineInstr *DefMI, bool FindMin) const; 833 const MachineInstr *DefMI, unsigned DefIdx, 842 const MachineInstr *DefMI, unsigned DefIdx) const = 0; 1016 const MachineInstr *DefMI, unsigne 831 hasHighOperandLatency(const InstrItineraryData *ItinData, const MachineRegisterInfo *MRI, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument [all...] |
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/X86/ |
H A D | X86InstrInfo.h | 375 const MachineInstr *DefMI, unsigned DefIdx, 397 /// defined by the load we are trying to fold. DefMI returns the machine 403 MachineInstr *&DefMI) const;
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/macosx-10.9.5/llvmCore-3425.0.33/lib/CodeGen/SelectionDAG/ |
H A D | InstrEmitter.cpp | 483 MachineInstr *DefMI = MRI->getVRegDef(VReg); 485 if (DefMI && 486 TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) &&
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