Searched refs:AL (Results 1 - 25 of 65) sorted by relevance

123

/macosx-10.9.5/WebCore-7537.78.1/rendering/
H A Dbreak_lines.cpp67 #define AL { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } macro
101 AL, AL, AL, AL, AL, AL, AL, AL, AL, A
119 #undef AL macro
[all...]
/macosx-10.9.5/ICU-511.35/icuSources/test/cintltst/
H A Dcbididat.c23 "LRE", "LRO", "AL", "RLE", "RLO", "PDF", "NSM", "BN"
30 /* LRE LRO AL RLE RLO PDF NSM BN */
51 R, AL, WS, R, AL, WS, R
81 L, AL, AL, AL, L, AL, AL, L, WS, EN, CS, WS, EN, CS, EN, WS, L, L
96 AL,
[all...]
H A Dcbiditst.h48 #define AL U_RIGHT_TO_LEFT_ARABIC macro
/macosx-10.9.5/JavaScriptCore-7537.78.1/assembler/
H A DARMAssembler.h124 AL = 0xe0000000 // Unconditional / Always execute. enumerator in enum:JSC::ARMAssembler::__anon2639
271 void bitAnd(int rd, int rn, ARMWord op2, Condition cc = AL) argument
276 void bitAnds(int rd, int rn, ARMWord op2, Condition cc = AL) argument
281 void eor(int rd, int rn, ARMWord op2, Condition cc = AL) argument
286 void eors(int rd, int rn, ARMWord op2, Condition cc = AL) argument
291 void sub(int rd, int rn, ARMWord op2, Condition cc = AL) argument
296 void subs(int rd, int rn, ARMWord op2, Condition cc = AL) argument
301 void rsb(int rd, int rn, ARMWord op2, Condition cc = AL) argument
306 void rsbs(int rd, int rn, ARMWord op2, Condition cc = AL) argument
311 void add(int rd, int rn, ARMWord op2, Condition cc = AL) argument
316 adds(int rd, int rn, ARMWord op2, Condition cc = AL) argument
321 adc(int rd, int rn, ARMWord op2, Condition cc = AL) argument
326 adcs(int rd, int rn, ARMWord op2, Condition cc = AL) argument
331 sbc(int rd, int rn, ARMWord op2, Condition cc = AL) argument
336 sbcs(int rd, int rn, ARMWord op2, Condition cc = AL) argument
341 rsc(int rd, int rn, ARMWord op2, Condition cc = AL) argument
346 rscs(int rd, int rn, ARMWord op2, Condition cc = AL) argument
351 tst(int rn, ARMWord op2, Condition cc = AL) argument
356 teq(int rn, ARMWord op2, Condition cc = AL) argument
361 cmp(int rn, ARMWord op2, Condition cc = AL) argument
366 cmn(int rn, ARMWord op2, Condition cc = AL) argument
371 orr(int rd, int rn, ARMWord op2, Condition cc = AL) argument
376 orrs(int rd, int rn, ARMWord op2, Condition cc = AL) argument
381 mov(int rd, ARMWord op2, Condition cc = AL) argument
387 movw(int rd, ARMWord op2, Condition cc = AL) argument
393 movt(int rd, ARMWord op2, Condition cc = AL) argument
400 movs(int rd, ARMWord op2, Condition cc = AL) argument
405 bic(int rd, int rn, ARMWord op2, Condition cc = AL) argument
410 bics(int rd, int rn, ARMWord op2, Condition cc = AL) argument
415 mvn(int rd, ARMWord op2, Condition cc = AL) argument
420 mvns(int rd, ARMWord op2, Condition cc = AL) argument
425 mul(int rd, int rn, int rm, Condition cc = AL) argument
430 muls(int rd, int rn, int rm, Condition cc = AL) argument
435 mull(int rdhi, int rdlo, int rn, int rm, Condition cc = AL) argument
440 vmov_f64(int dd, int dm, Condition cc = AL) argument
445 vadd_f64(int dd, int dn, int dm, Condition cc = AL) argument
450 vdiv_f64(int dd, int dn, int dm, Condition cc = AL) argument
455 vsub_f64(int dd, int dn, int dm, Condition cc = AL) argument
460 vmul_f64(int dd, int dn, int dm, Condition cc = AL) argument
465 vcmp_f64(int dd, int dm, Condition cc = AL) argument
470 vsqrt_f64(int dd, int dm, Condition cc = AL) argument
475 vabs_f64(int dd, int dm, Condition cc = AL) argument
480 vneg_f64(int dd, int dm, Condition cc = AL) argument
485 ldrImmediate(int rd, ARMWord imm, Condition cc = AL) argument
490 ldrUniqueImmediate(int rd, ARMWord imm, Condition cc = AL) argument
495 dtrUp(DataTransferTypeA transferType, int rd, int rb, ARMWord op2, Condition cc = AL) argument
500 dtrUpRegister(DataTransferTypeA transferType, int rd, int rb, int rm, Condition cc = AL) argument
505 dtrDown(DataTransferTypeA transferType, int rd, int rb, ARMWord op2, Condition cc = AL) argument
510 dtrDownRegister(DataTransferTypeA transferType, int rd, int rb, int rm, Condition cc = AL) argument
515 halfDtrUp(DataTransferTypeB transferType, int rd, int rb, ARMWord op2, Condition cc = AL) argument
520 halfDtrUpRegister(DataTransferTypeB transferType, int rd, int rn, int rm, Condition cc = AL) argument
525 halfDtrDown(DataTransferTypeB transferType, int rd, int rb, ARMWord op2, Condition cc = AL) argument
530 halfDtrDownRegister(DataTransferTypeB transferType, int rd, int rn, int rm, Condition cc = AL) argument
535 doubleDtrUp(DataTransferTypeFloat type, int rd, int rb, ARMWord op2, Condition cc = AL) argument
542 doubleDtrDown(DataTransferTypeFloat type, int rd, int rb, ARMWord op2, Condition cc = AL) argument
549 push(int reg, Condition cc = AL) argument
555 pop(int reg, Condition cc = AL) argument
561 poke(int reg, Condition cc = AL) argument
566 peek(int reg, Condition cc = AL) argument
571 vmov_vfp64(int sm, int rt, int rt2, Condition cc = AL) argument
577 vmov_arm64(int rt, int rt2, int sm, Condition cc = AL) argument
583 vmov_vfp32(int sn, int rt, Condition cc = AL) argument
589 vmov_arm32(int rt, int sn, Condition cc = AL) argument
595 vcvt_f64_s32(int dd, int sm, Condition cc = AL) argument
601 vcvt_s32_f64(int sd, int dm, Condition cc = AL) argument
607 vcvt_u32_f64(int sd, int dm, Condition cc = AL) argument
613 vcvt_f64_f32(int dd, int sm, Condition cc = AL) argument
619 vcvt_f32_f64(int dd, int sm, Condition cc = AL) argument
625 vmrs_apsr(Condition cc = AL) argument
630 clz(int rd, int rm, Condition cc = AL) argument
645 bx(int rm, Condition cc = AL) argument
650 blx(int rm, Condition cc = AL) argument
750 loadBranchTarget(int rd, Condition cc = AL, int useConstantPool = 0) argument
758 jmp(Condition cc = AL, int useConstantPool = 0) argument
[all...]
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/ARM/
H A DThumb2RegisterInfo.h36 ARMCC::CondCodes Pred = ARMCC::AL,
H A DThumb2RegisterInfo.cpp50 .addConstantPoolIndex(Idx).addImm((int64_t)ARMCC::AL).addReg(0)
H A DThumb1RegisterInfo.h42 ARMCC::CondCodes Pred = ARMCC::AL,
H A DARMAsmPrinter.cpp1052 BrInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1331 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1352 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1361 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1374 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1386 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1401 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1415 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1450 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1487 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
[all...]
H A DARMInstrInfo.cpp40 NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
46 NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
H A DThumb2InstrInfo.cpp39 NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
63 if (CC != ARMCC::AL)
71 if (CC != ARMCC::AL) {
109 return getITInstrPredicate(MBBI, PredReg) == ARMCC::AL;
404 if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
570 return ARMCC::AL;
H A DThumb1InstrInfo.cpp33 NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
H A DThumb2ITBlockPass.cpp171 if (CC == ARMCC::AL) {
214 if (NCC == ARMCC::AL &&
H A DARMBaseRegisterInfo.h168 ARMCC::CondCodes Pred = ARMCC::AL,
H A DARMBaseInstrInfo.h80 : ARMCC::AL;
321 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
362 /// condition, otherwise returns AL. It also returns the condition code
H A DThumb2SizeReduction.cpp258 if (Pred == ARMCC::AL) {
510 if (MI->getOperand(3).getImm() != ARMCC::AL)
545 if (getInstrPredicate(MI, PredReg) == ARMCC::AL) {
646 if (Pred != ARMCC::AL) {
738 if (Pred != ARMCC::AL) {
/macosx-10.9.5/screen-22/screen/etc/
H A Detcscreenrc32 # AL add multiple lines
48 termcap facit al=\E[L\E[K:AL@:dl@:DL@:cs=\E[%i%d;%dr:ic@
49 terminfo facit al=\E[L\E[K:AL@:dl@:DL@:cs=\E[%i%p1%d;%p2%dr:ic@
52 termcap sun 'up=^K:AL=\E[%dL:DL=\E[%dM:UP=\E[%dA:DO=\E[%dB:LE=\E[%dD:RI=\E[%dC:IC=\E[%d@:WS=1000\E[8;%d;%dt'
53 terminfo sun 'up=^K:AL=\E[%p1%dL:DL=\E[%p1%dM:UP=\E[%p1%dA:DO=\E[%p1%dB:LE=\E[%p1%dD:RI=\E[%p1%dC:IC=\E[%p1%d@:WS=\E[8;%p1%d;%p2%dt$<1000>'
H A Dscreenrc100 termcap vt100* ms:AL=\E[%dL:DL=\E[%dM:UP=\E[%dA:DO=\E[%dB:LE=\E[%dD:RI=\E[%dC
101 terminfo vt100* ms:AL=\E[%p1%dL:DL=\E[%p1%dM:UP=\E[%p1%dA:DO=\E[%p1%dB:LE=\E[%p1%dD:RI=\E[%p1%dC
/macosx-10.9.5/system_cmds-597.90.1/getty.tproj/
H A Dmain.c381 if (AL) {
382 const char *p = AL;
405 } else if (rval || AL) {
418 if (AL) {
420 "invalid auto-login name: %s", AL);
450 execle(LO, "login", AL ? "-fp1" : "-p1", name,
452 execle(LO, "login", AL ? "-fp" : "-p", name,
/macosx-10.9.5/system_cmds-597.90.1/system_cmds-597.1.1/getty.tproj/
H A Dmain.c381 if (AL) {
382 const char *p = AL;
405 } else if (rval || AL) {
418 if (AL) {
420 "invalid auto-login name: %s", AL);
450 execle(LO, "login", AL ? "-fp1" : "-p1", name,
452 execle(LO, "login", AL ? "-fp" : "-p", name,
/macosx-10.9.5/ICU-511.35/icuSources/common/
H A Dubidiimp.h50 AL= U_RIGHT_TO_LEFT_ARABIC, enumerator in enum:__anon989
72 #define MASK_RTL (DIRPROP_FLAG(R)|DIRPROP_FLAG(AL)|DIRPROP_FLAG(RLE)|DIRPROP_FLAG(RLO))
73 #define MASK_R_AL (DIRPROP_FLAG(R)|DIRPROP_FLAG(AL))
275 /* lastArabicPos is index to the last AL in the text, -1 if none */
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/ARM/MCTargetDesc/
H A DARMBaseInfo.h44 AL // Always (unconditional) Always (unconditional) enumerator in enum:llvm::ARMCC::CondCodes
84 case ARMCC::AL: return "al";
H A DARMMCTargetDesc.cpp211 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
218 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
/macosx-10.9.5/vim-53/runtime/
H A Dtermcap17 :AL=\E[%dL:DL=\E[%dM:IC=\E[%d@:DC=\E[%dP:\
65 :al=\E[L:AL=\E[%dL:dl=\E[M:DL=\E[%dM:le=^H:cm=\E[%i%d;%dH:\
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/X86/
H A DX86SelectionDAGInfo.cpp112 ValReg = X86::AL;
129 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, Src, InFlag);
H A DX86RegisterInfo.cpp622 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
634 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
635 return X86::AL;
671 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
707 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
759 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:

Completed in 301 milliseconds

123