Searched refs:rdmsr64 (Results 1 - 9 of 9) sorted by relevance

/macosx-10.5.8/xnu-1228.15.4/osfmk/i386/
H A Dmachine_check.c88 ia32_mcg_cap.u64 = rdmsr64(IA32_MCG_CAP);
194 rdmsr64(IA32_MCG_CTL) : 0ULL;
195 mca_state->mca_mcg_status.u64 = rdmsr64(IA32_MCG_STATUS);
199 bank->mca_mci_ctl = rdmsr64(IA32_MCi_CTL(i));
200 bank->mca_mci_status.u64 = rdmsr64(IA32_MCi_STATUS(i));
204 rdmsr64(IA32_MCi_MISC(i)) : 0ULL;
206 rdmsr64(IA32_MCi_ADDR(i)) : 0ULL;
227 kdb_printf(" IA32_MCG_RAX: 0x%016qx\n", rdmsr64(IA32_MCG_RAX));
228 kdb_printf(" IA32_MCG_RBX: 0x%016qx\n", rdmsr64(IA32_MCG_RBX));
229 kdb_printf(" IA32_MCG_RCX: 0x%016qx\n", rdmsr64(IA32_MCG_RC
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H A Dmtrr.c132 range[i].base = rdmsr64(MSR_IA32_MTRR_PHYSBASE(i));
133 range[i].mask = rdmsr64(MSR_IA32_MTRR_PHYSMASK(i));
166 range[0].types = rdmsr64(MSR_IA32_MTRR_FIX64K_00000);
167 range[1].types = rdmsr64(MSR_IA32_MTRR_FIX16K_80000);
168 range[2].types = rdmsr64(MSR_IA32_MTRR_FIX16K_A0000);
170 range[3 + i].types = rdmsr64(MSR_IA32_MTRR_FIX4K_C0000 + i);
194 int count = rdmsr64(MSR_IA32_MTRRCAP) & IA32_MTRRCAP_VCNT;
199 rdmsr64(MSR_IA32_MTRR_PHYSBASE(i)),
200 rdmsr64(MSR_IA32_MTRR_PHYSMASK(i)),
201 MASK_TO_LEN(rdmsr64(MSR_IA32_MTRR_PHYSMAS
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H A Dperfmon.c277 cccr.u_u64 = rdmsr64(cccr_addr);
281 rdmsr64(pmc_table->msr_counter_base + id);
322 ovf_status.u64 = rdmsr64(pmc_table->Core.msr_global_status);
462 ctrl.u64 = rdmsr64(pmc_table->Core.msr_global_ctrl);
502 ctrl.u64 = rdmsr64(pmc_table->Core.msr_global_ctrl);
524 *(uint64_t *)val = rdmsr64(pmc_table->msr_counter_base + id);
553 *(uint64_t *)cccr = rdmsr64(pmc_table->msr_control_base + id);
586 evtsel->u64 = rdmsr64(pmc_table->msr_control_base + id);
627 *(uint64_t *)escr = rdmsr64(addr);
H A Dstartup64.c75 (rdmsr64(MSR_IA32_EFER) & MSR_IA32_EFER_LMA) != 0)
122 if ((rdmsr64(MSR_IA32_EFER) & MSR_IA32_EFER_LMA) == 0)
138 (rdmsr64(MSR_IA32_EFER) & MSR_IA32_EFER_LMA) == 0)
181 if ((rdmsr64(MSR_IA32_EFER) & MSR_IA32_EFER_LMA) != 0)
H A Dtsc.c158 msr_flex_ratio = rdmsr64(MSR_FLEX_RATIO);
159 msr_platform_info = rdmsr64(MSR_PLATFORM_INFO);
188 prfsts = rdmsr64(IA32_PERF_STS);
H A Dproc_reg.h285 static inline uint64_t rdmsr64(uint32_t msr) function
H A Dcpuid.c388 (uint32_t) (rdmsr64(MSR_IA32_BIOS_SIGN_ID) >> 32);
395 uint64_t msr_core_thread_count = rdmsr64(MSR_CORE_THREAD_COUNT);
H A Dmp_desc.c440 wrmsr64(MSR_IA32_EFER, rdmsr64(MSR_IA32_EFER) | MSR_IA32_EFER_SCE);
468 rdmsr64(MSR_IA32_KERNEL_GS_BASE));
/macosx-10.5.8/xnu-1228.15.4/osfmk/i386/vmx/
H A Dvmx_cpu.c65 (rdmsr64(MSR_IA32_FEATURE_CONTROL) & MSR_IA32_FEATCTL_VMXON));
102 msr_image = rdmsr64(MSR_IA32_FEATURE_CONTROL);
144 msr_image = rdmsr64(MSR_IA32_VMX_BASIC);
150 msr_image = rdmsr64(MSR_IA32_VMXPINBASED_CTLS);
155 msr_image = rdmsr64(MSR_IA32_PROCBASED_CTLS);
160 msr_image = rdmsr64(MSR_IA32_VMX_EXIT_CTLS);
165 msr_image = rdmsr64(MSR_IA32_VMX_ENTRY_CTLS);
170 msr_image = rdmsr64(MSR_IA32_VMX_MISC);
180 specs->cr0_fixed_0 = rdmsr64(MSR_IA32_VMX_CR0_FIXED0) & 0xFFFFFFFF;
181 specs->cr0_fixed_1 = rdmsr64(MSR_IA32_VMX_CR0_FIXED
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