Searched refs:MASK (Results 1 - 25 of 28) sorted by relevance

12

/macosx-10.5.8/xnu-1228.15.4/osfmk/ppc/
H A Dproc_reg.h53 #undef MASK macro
54 #define MASK(PART) MASK32(PART) macro
96 #define MSR_SUPERVISOR_INT_OFF (MASK(MSR_ME) | MASK(MSR_IR) | MASK(MSR_DR))
99 #define MSR_SUPERVISOR_INT_ON (MSR_SUPERVISOR_INT_OFF | MASK(MSR_EE))
102 #define MSR_VM_OFF (MASK(MSR_ME))
105 #define MSR_PHYS_INST_VIRT_DATA (MASK(MSR_ME) | MASK(MSR_IR))
110 #define MSR_EXPORT_MASK_SET (MASK(MSR_E
[all...]
H A Dtrap.c179 intr = (ssp->save_srr1 & MASK(MSR_EE)) != 0; /* Remember if we were enabled */
274 if (ssp->save_srr1 & MASK(SRR1_PRG_TRAP)) {
341 dsisr & MASK(DSISR_WRITE) ? PROT_RW : PROT_RO,
349 ~((MASK(DSISR_NOEX) | MASK(DSISR_PROT)))) | MASK(DSISR_HASH); /* Make sure this is marked as a miss */
377 dsisr & MASK(DSISR_WRITE) ? PROT_RW : PROT_RO,
394 ~((MASK(DSISR_NOEX) | MASK(DSISR_PROT)))) | MASK(DSISR_HAS
[all...]
H A Ddb_asm.s52 lis r7,hi16(MASK(MSR_VEC))
53 ori r7,r7,lo16(MASK(MSR_FP))
56 ori r7,r7,lo16(MASK(MSR_DR)) ; Set the DR bit
H A Dstatus.c787 genuser->save_srr1 &= ~(MASK(MSR_FP) | MASK(MSR_VEC)); /* Make sure we don't enable the floating point unit */
845 genuser->save_srr1 &= ~(MASK(MSR_FP) | MASK(MSR_VEC)); /* Make sure we don't enable the floating point unit */
1051 sv->save_srr1 &= (uint64_t)(~(MASK(MSR_FP) | MASK(MSR_VEC))); /* Make certain that floating point and vector are turned off */
1387 sv->save_srr1 |= MASK(MSR_SE);
1389 sv->save_srr1 &= ~MASK(MSR_SE);
1484 return (MASK(MSR_POW)|MASK(MSR_IL
[all...]
H A Dmisc_asm.s62 lis r8,hi16(MASK(MSR_VEC)) ; Get the vector flag
64 ori r8,r8,lo16(MASK(MSR_EE)|MASK(MSR_FP)) ; Add the FP flag
90 lis r8,hi16(MASK(MSR_VEC)) ; Get the vector flag
92 ori r8,r8,lo16(MASK(MSR_EE)|MASK(MSR_FP)) ; Add the FP flag
H A Ddb_machdep.h88 #define db_clear_single_step(regs) ((regs)->save_srr1 &= ~MASK(MSR_SE))
89 #define db_set_single_step(regs) ((regs)->save_srr1 |= MASK(MSR_SE))
H A Dmovc.s164 lis r2,hi16(MASK(MSR_VEC)) ; Get the vector flag
166 ori r2,r2,lo16(MASK(MSR_FP)) ; Add the FP flag
172 ori r2,r2,lo16(MASK(MSR_EE)) // Get EE on also
175 ori r2,r2,MASK(MSR_FP) // must enable FP for G3...
177 oris r2,r2,hi16(MASK(MSR_VEC)) // enable altivec for G4 (ignored if G3)
320 li r0,MASK(MSR_DR) // get DR bit
393 li r0,MASK(MSR_DR) // get DR bit
1078 lis r0,hi16(MASK(MSR_VEC)) // get vector mask
1079 ori r0,r0,lo16(MASK(MSR_FP)) // insert fp mask
1082 ori r0,r0,lo16(MASK(MSR_E
[all...]
H A Dmachine_routines_asm.s58 ori r0,r0,lo16(MASK(MSR_EE)+MASK(MSR_FP)+MASK(MSR_IR)+MASK(MSR_DR)) // turn off all 4
60 oris r0,r0,hi16(MASK(MSR_VEC)) // Turn off vector too
76 ori r0,r0,lo16(MASK(MSR_EE)) // turn EE and fp off
93 oris r0,r0,hi16(MASK(MSR_VEC)) // Always gonna turn of vectors
95 ori r0,r0,lo16(MASK(MSR_DR)+MASK(MSR_FP)) // always turn off DR and FP bit
157 mpr32bit: lis r8,hi16(MASK(MSR_VE
[all...]
H A Dhw_lock.s198 lis r0,hi16(MASK(MSR_VEC)) ; Get vector enable
200 ori r0,r0,lo16(MASK(MSR_FP)) ; Get FP enable
201 ori r7,r0,lo16(MASK(MSR_EE)) ; Get EE bit on too
340 lis r0,hi16(MASK(MSR_VEC)) ; Get vector enable
342 ori r0,r0,lo16(MASK(MSR_FP)) ; Get FP enable
343 ori r8,r0,lo16(MASK(MSR_EE)) ; Get EE bit on too
475 lis r0,hi16(MASK(MSR_VEC)) ; Get vector enable
477 ori r0,r0,lo16(MASK(MSR_FP)) ; Get FP enable
478 ori r7,r0,lo16(MASK(MSR_EE)) ; Get EE bit on too
934 lis r0,hi16(MASK(MSR_VE
[all...]
H A DPseudoKernel.c197 sv->save_srr1 &= ~(MASK(MSR_BE)|MASK(MSR_SE)); /* Clear SE|BE bits in MSR */
H A Dhw_exception.s231 lis r10,hi16(MASK(MSR_VEC)) ; Get the vector enable
233 ori r10,r10,lo16(MASK(MSR_FP)|MASK(MSR_EE)) ; Add in FP and EE
421 ori r11,r11,lo16(MASK(MSR_EE)) ; Turn on interruption enabled bit
676 lis r10,hi16(MASK(MSR_VEC)) ; Get the vector enable
678 ori r10,r10,lo16(MASK(MSR_FP)|MASK(MSR_EE)) ; Add in FP and EE
699 andi. r3,r3,MASK(MSR_PR)
781 lis r10,hi16(MASK(MSR_VEC)) ; Get the vector enable
783 ori r10,r10,lo16(MASK(MSR_F
[all...]
H A DFirmware.s197 li r8,lo16(MASK(MSR_DR)) ; Get the DR bit
199 ori r8,r8,lo16(MASK(MSR_EE)) ; Add in the EE bit
221 lis r2,hi16(MASK(MSR_VEC)) ; Get the vector enable
223 ori r2,r2,lo16(MASK(MSR_FP)) ; Get the FP enable
1974 lis r2,hi16(MASK(MSR_VEC)) ; Get the vector enable
1976 ori r2,r2,lo16(MASK(MSR_FP)) ; Get the FP enable
2015 lis r2,hi16(MASK(MSR_VEC)) ; Get the vector enable
2017 ori r2,r2,lo16(MASK(MSR_FP)) ; Get the FP enable
2018 ori r4,r4,lo16(MASK(MSR_EE)) ; Get the EE bit
2023 ori r4,r4,lo16(MASK(MSR_F
[all...]
H A Dmodel_dep.c473 if(!(sv->save_srr1 & MASK(MSR_PR))) { /* Are we in the kernel? */
795 if (saved_state->save_srr1 & MASK(SRR1_PRG_TRAP)) { /* Trap instruction? */
H A Dcswtch.s196 ori r6,r6,lo16(MASK(MSR_FP)) ; Enable floating point
244 oris r6,r6,hi16(MASK(MSR_VEC)) ; Enable vector
290 li r10,(MASK(MSR_ME)|MASK(MSR_DR)) /* Get the switcher's MSR */
387 lis r2,hi16(MASK(MSR_VEC)) ; Get the vector enable
388 li r12,lo16(MASK(MSR_EE)) ; Get the EE bit
389 ori r2,r2,lo16(MASK(MSR_FP)) ; Get FP
394 ori r2,r2,MASK(MSR_FP) ; Enable the floating point feature for now also
559 ori r19,r19,lo16(MASK(MSR_FP)) ; Enable the floating point feature
871 ori r8,r8,MASK(MSR_F
[all...]
H A Dlowmem_vectors.s903 rlwinm r20,r20,MSR_PR_BIT-enaUsrFCallb,MASK(MSR_PR) ; Shift the validity bit over to pr bit spot
909 andi. r20,r20,MASK(MSR_PR) ; Set cr0_eq is we are in problem state and the validity bit is not set
1041 rlwinm r20,r20,MSR_PR_BIT-enaUsrFCallb,MASK(MSR_PR) ; Shift the validity bit over to pr bit spot
1047 andi. r20,r20,MASK(MSR_PR) ; Set cr0_eq when we are in problem state and the validity bit is not set
1282 lis r4,hi16(MASK(MSR_VEC)|MASK(MSR_FP)|MASK(MSR_ME)) ; Set up the MSR we will use throughout. Note that ME come on here if MCK
1284 ori r4,r4,lo16(MASK(MSR_VEC)|MASK(MSR_FP)|MASK(MSR_M
[all...]
H A Dvmachmon_asm.s514 lis r2,hi16(MASK(DSISR_HASH)) ; Set PTE/DBAT miss
729 lis r7,hi16(MASK(DSISR_HASH)) ; Pretend like we got a PTE miss
1685 lis r2,hi16(MASK(DSISR_HASH)) ; Set PTE/DBAT miss
1728 lis r2,hi16(MASK(DSISR_HASH)) ; Set PTE/DBAT miss
1811 li r6,lo16(MASK(MSR_FE0)|MASK(MSR_SE)|MASK(MSR_BE)|MASK(MSR_FE1))
1881 li r6,lo16(MASK(MSR_FE0)|MASK(MSR_S
[all...]
H A Dbcopy.s176 lis r6,hi16(MASK(MSR_VEC)) ; Get vector enable
177 ori r6,r6,lo16(MASK(MSR_FP)|MASK(MSR_DR)) ; Add in FP and DR
189 ori r9,r9,lo16(MASK(MSR_DR)) ; turn translation back on (but leave VEC and FP off)
201 ori r8,r9,lo16(MASK(MSR_DR)) ; make a copy with DR back on... this is what we return to caller
219 ori r9,r9,lo16(MASK(MSR_DR)) ; turn translation back on
H A Dmachine_routines.c314 return((mfmsr() & MASK(MSR_EE)) != 0);
/macosx-10.5.8/xnu-1228.15.4/bsd/ppc/
H A Dparam.h122 #ifndef MASK
123 #define MASK(PART) ENDIAN_MASK(PART ## _BIT, 32) macro
128 #define USERMODE(msr) (msr & MASK(MSR_PR) ? TRUE : FALSE)
129 #define BASEPRI(msr) (msr & MASK(MSR_EE) ? TRUE : FALSE)
/macosx-10.5.8/xnu-1228.15.4/osfmk/kdp/ml/ppc/
H A Dkdp_asm.s47 lis r2,hi16(MASK(MSR_VEC)) ; Get the vector enable
49 ori r2,r2,lo16(MASK(MSR_EE)|MASK(MSR_FP)) ; Get FP and EE
78 lis r2,hi16(MASK(MSR_VEC)) ; Get the vector enable
80 ori r2,r2,lo16(MASK(MSR_EE)|MASK(MSR_FP)) ; Get FP and EE
H A Dkdp_machdep.c595 if(saved_state->save_srr1 & (MASK(MSR_SE) | MASK(MSR_BE))) { /* Are we just stepping or continuing */
/macosx-10.5.8/xnu-1228.15.4/osfmk/i386/
H A Dlapic.c245 #define MASK(lvt) \ macro
272 MASK(LVT_CMCI));
276 MASK(LVT_TIMER),
285 MASK(LVT_PERFCNT));
290 MASK(LVT_THERMAL));
297 MASK(LVT_LINT0));
304 MASK(LVT_LINT1));
308 MASK(LVT_ERROR));
/macosx-10.5.8/xnu-1228.15.4/osfmk/ppc/commpage/
H A Dcommpage_asm.s117 ori r2,r11,MASK(MSR_FP) // turn FP on
/macosx-10.5.8/xnu-1228.15.4/bsd/nfs/
H A Dnfsm_subs.h443 #define nfsm_chain_add_bitmap_masked(E, NMC, B, LEN, MASK) \
448 nfsm_chain_add_32((E), (NMC), ((B)[__i] & (MASK)[__i])); \
/macosx-10.5.8/xnu-1228.15.4/osfmk/chud/ppc/
H A Dchud_thread_ppc.c426 #define USER_MODE(msr) ((msr) & MASK(MSR_PR) ? TRUE : FALSE)
430 #define SUPERVISOR_MODE(msr) ((msr) & MASK(MSR_PR) ? FALSE : TRUE)

Completed in 95 milliseconds

12