/macosx-10.10.1/ruby-106/ruby/template/ |
H A D | insns_info.inc.tmpl | 34 insn_stack_increase(int depth, int insn, VALUE *opes) 36 switch(insn){ 48 insn_len(VALUE insn) 50 return insn_len_info[(int)insn]; 54 insn_name(VALUE insn) 56 return insn_name_info[(int)insn]; 60 insn_op_types(VALUE insn) 62 return insn_operand_info[(int)insn]; 66 insn_op_type(VALUE insn, long pos) 68 int len = insn_len(insn) [all...] |
/macosx-10.10.1/cxxfilt-11/cxxfilt/include/opcode/ |
H A D | spu.h | 91 #define SIGNED_EXTRACT(insn,size,pos) (((int)((insn) << (32-size-pos))) >> (32-size)) 92 #define UNSIGNED_EXTRACT(insn,size,pos) (((insn) >> pos) & ((1 << size)-1)) 94 #define DECODE_INSN_RT(insn) (insn & 0x7f) 95 #define DECODE_INSN_RA(insn) ((insn >> 7) & 0x7f) 96 #define DECODE_INSN_RB(insn) ((insn >> 1 [all...] |
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/X86/Disassembler/ |
H A D | X86DisassemblerDecoder.c | 166 * @param insn - The instruction with the reader function to use. The cursor 172 static int consumeByte(struct InternalInstruction* insn, uint8_t* byte) { argument 173 int ret = insn->reader(insn->readerArg, byte, insn->readerCursor); 176 ++(insn->readerCursor); 184 * @param insn - See consumeByte(). 188 static int lookAtByte(struct InternalInstruction* insn, uint8_t* byte) { argument 189 return insn->reader(insn 192 unconsumeByte(struct InternalInstruction* insn) argument 239 dbgprintf(struct InternalInstruction* insn, const char* format, ...) argument 266 setPrefixPresent(struct InternalInstruction* insn, uint8_t prefix, uint64_t location) argument 283 isPrefixAtLocation(struct InternalInstruction* insn, uint8_t prefix, uint64_t location) argument 303 readPrefixes(struct InternalInstruction* insn) argument 540 readOpcode(struct InternalInstruction* insn) argument 659 getIDWithAttrMask(uint16_t* instructionID, struct InternalInstruction* insn, uint8_t attrMask) argument 726 getID(struct InternalInstruction* insn, const void *miiArg) argument 923 readSIB(struct InternalInstruction* insn) argument 1021 readDisplacement(struct InternalInstruction* insn) argument 1066 readModRM(struct InternalInstruction* insn) argument 1277 fixupReg(struct InternalInstruction *insn, const struct OperandSpecifier *op) argument 1327 readOpcodeModifier(struct InternalInstruction* insn) argument 1362 readOpcodeRegister(struct InternalInstruction* insn, uint8_t size) argument 1412 readImmediate(struct InternalInstruction* insn, uint8_t size) argument 1466 readVVVV(struct InternalInstruction* insn) argument 1489 readOperands(struct InternalInstruction* insn) argument 1626 decodeInstruction(struct InternalInstruction* insn, byteReader_t reader, const void* readerArg, dlog_t logger, void* loggerArg, const void* miiArg, uint64_t startLoc, DisassemblerMode mode) argument [all...] |
H A D | X86Disassembler.cpp | 316 /// @param insn - The internal instruction. 319 InternalInstruction &insn, 329 pcrel = insn.startLocation + 330 insn.immediateOffset + insn.immediateSize; 331 switch (insn.displacementSize) { 392 pcrel = insn.startLocation + insn.immediateOffset + insn.immediateSize; 405 pcrel = insn 317 translateImmediate(MCInst &mcInst, uint64_t immediate, const OperandSpecifier &operand, InternalInstruction &insn, const MCDisassembler *Dis) argument 429 translateRMRegister(MCInst &mcInst, InternalInstruction &insn) argument 467 translateRMMemory(MCInst &mcInst, InternalInstruction &insn, const MCDisassembler *Dis) argument 650 translateRM(MCInst &mcInst, const OperandSpecifier &operand, InternalInstruction &insn, const MCDisassembler *Dis) argument 720 translateOperand(MCInst &mcInst, const OperandSpecifier &operand, InternalInstruction &insn, const MCDisassembler *Dis) argument 778 translateInstruction(MCInst &mcInst, InternalInstruction &insn, const MCDisassembler *Dis) argument [all...] |
/macosx-10.10.1/libpcap-48/libpcap/ |
H A D | bpf_dump.c | 36 const struct bpf_insn *insn; local 40 insn = p->bf_insns; 43 for (i = 0; i < n; ++insn, ++i) { 44 printf("%u %u %u %u\n", insn->code, 45 insn->jt, insn->jf, insn->k); 50 for (i = 0; i < n; ++insn, ++i) 52 insn->code, insn [all...] |
/macosx-10.10.1/tcpdump-61/tcpdump/ |
H A D | bpf_dump.c | 40 struct bpf_insn *insn; local 44 insn = p->bf_insns; 47 for (i = 0; i < n; ++insn, ++i) { 48 printf("%u %u %u %u\n", insn->code, 49 insn->jt, insn->jf, insn->k); 54 for (i = 0; i < n; ++insn, ++i) 56 insn->code, insn [all...] |
/macosx-10.10.1/ruby-106/ruby/ |
H A D | vm_exec.h | 29 #define DEBUG_ENTER_INSN(insn) \ 44 #define DEBUG_ENTER_INSN(insn) 61 #define INSN_ENTRY(insn) \ 63 FUNC_FASTCALL(LABEL(insn))(rb_thread_t *th, rb_control_frame_t *reg_cfp) { 65 #define END_INSN(insn) return reg_cfp;} 77 #define INSN_ENTRY_SIG(insn) 80 #define INSN_DISPATCH_SIG(insn) 82 #define INSN_ENTRY(insn) \ 83 LABEL(insn): \ 84 INSN_ENTRY_SIG(insn); \ [all...] |
/macosx-10.10.1/cxxfilt-11/cxxfilt/opcodes/ |
H A D | m10200-dis.c | 29 unsigned long insn, 66 if ((op->mask & insn) == op->opcode 87 value = (insn & 0xffff) << 8; 92 value = ((insn >> (operand->shift)) 109 value = ((insn >> (operand->shift + extra_shift)) 116 value = ((insn >> (operand->shift + extra_shift)) 156 (*info->fprintf_func) (info->stream, _("unknown\t0x%04lx"), insn); 164 unsigned long insn; local 176 insn = *(unsigned char *) buffer; 179 if ((insn 27 disassemble(bfd_vma memaddr, struct disassemble_info *info, unsigned long insn, unsigned long extension, unsigned int size) argument [all...] |
H A D | m10300-dis.c | 34 unsigned long insn, 75 if ((op->mask & insn) == op->opcode 114 insn &= 0xff0000; 122 insn |= bfd_getl16 (buffer); 138 insn &= 0xffff0000; 146 insn |= bfd_getl16 (buffer); 161 insn &= 0xff000000; 162 insn |= (temp & 0xffffff00) >> 8; 173 insn &= 0xffff0000; 174 insn | 32 disassemble(bfd_vma memaddr, struct disassemble_info *info, unsigned long insn, unsigned int size) argument 588 unsigned long insn; local [all...] |
H A D | avr-dis.c | 47 avr_operand (unsigned int insn, unsigned int insn2, unsigned int pc, int constraint, argument 58 insn = (insn & 0xf) | ((insn & 0x0200) >> 5); /* Source register. */ 60 insn = (insn & 0x01f0) >> 4; /* Destination register. */ 62 sprintf (buf, "r%d", insn); 67 sprintf (buf, "r%d", 16 + (insn & 0xf)); 69 sprintf (buf, "r%d", 16 + ((insn & 0xf0) >> 4)); 73 sprintf (buf, "r%d", 24 + ((insn 257 unsigned int insn, insn2; local [all...] |
H A D | hppa-dis.c | 163 #define GET_COMPL(insn) (GET_FIELD (insn, 26, 26) | \ 164 GET_FIELD (insn, 18, 18) << 1) 166 #define GET_COND(insn) (GET_FIELD ((insn), 16, 18) + \ 167 (GET_FIELD ((insn), 19, 19) ? 8 : 0)) 360 unsigned int insn, i; local 372 insn = bfd_getb32 (buffer); 378 if ((insn & opcode->mask) == opcode->match) 394 fput_reg (GET_FIELD (insn, 1 [all...] |
H A D | i860-dis.c | 93 unsigned int insn, i; local 106 insn = bfd_getl32 (buff); 113 if ((insn & opcode->match) == opcode->match 114 && (insn & opcode->lose) == 0) 125 (*info->fprintf_func) (info->stream, ".long %#08x", insn); 134 if (((insn & 0xfc000000) == 0x48000000 135 || (insn & 0xfc000000) == 0xb0000000) 136 && (insn & 0x200)) 148 grnames[(insn >> 11) & 0x1f]); 154 grnames[(insn >> 2 [all...] |
H A D | maxq-dis.c | 119 #define JUMP_CHECK(insn) \ 120 ( ((insn & _DECODE_4TO6_HIGHBYTE) == 0x0000) \ 121 || ((insn & _DECODE_4TO6_HIGHBYTE) == 0x2000) \ 122 || ((insn & _DECODE_4TO6_HIGHBYTE) == 0x6000) \ 123 || ((insn & _DECODE_4TO6_HIGHBYTE) == 0x1000) \ 124 || ((insn & _DECODE_4TO6_HIGHBYTE) == 0x5000) \ 125 || ((insn & _DECODE_4TO6_HIGHBYTE) == 0x3000) \ 126 || ((insn & _DECODE_4TO6_HIGHBYTE) == 0x7000) \ 127 || ((insn & _DECODE_4TO6_HIGHBYTE) == 0x4000) ) 354 get_group (const unsigned int insn) argument 411 get_insn_opcode(const unsigned int insn, group_info *i) argument 555 unsigned char insn[2], insn0, insn8, derived_code; local [all...] |
H A D | cgen-asm.in | 66 @arch@_cgen_build_insn_regex (CGEN_INSN *insn) 68 CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn); 69 const char *mnem = CGEN_INSN_MNEMONIC (insn); 87 /* Copy the literal mnemonic out of the insn. */ 157 CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t)); 158 reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB); 166 regerror (reg_err, (regex_t *) CGEN_INSN_RX (insn), msg, 80); 167 regfree ((regex_t *) CGEN_INSN_RX (insn)); 168 free (CGEN_INSN_RX (insn)); 169 (CGEN_INSN_RX (insn)) [all...] |
H A D | sparc-dis.c | 33 #define V9_ONLY_P(insn) (! ((insn)->architecture & ~MASK_V9)) 35 #define V9_P(insn) (((insn)->architecture & MASK_V9) != 0) 44 /* It is important that we only look at insn code bits as that is how the 191 is_delayed_branch (unsigned long insn) argument 195 for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next) 199 if ((opcode->match & insn) == opcode->match 200 && (opcode->lose & insn) == 0) 255 /* If one (and only one) insn is 455 unsigned long insn; local [all...] |
H A D | spu-dis.c | 53 get_index_for_opcode (unsigned int insn) argument 56 unsigned int opcode = insn >> (32-11); 98 unsigned int insn; local 109 insn = bfd_getb32 (buffer); 111 index = get_index_for_opcode (insn); 115 (*info->fprintf_func) (info->stream, ".long 0x%x", insn); 127 int fb = (insn >> (32-18)) & 0x7f; 148 DECODE_INSN_RT (insn)); 152 DECODE_INSN_RA (insn)); 156 DECODE_INSN_RB (insn)); [all...] |
H A D | tic80-dis.c | 98 #define M_SI(insn,op) ((((op)->flags & TIC80_OPERAND_M_SI) != 0) && ((insn) & (1 << 17))) 99 #define M_LI(insn,op) ((((op)->flags & TIC80_OPERAND_M_LI) != 0) && ((insn) & (1 << 15))) 100 #define R_SCALED(insn,op) ((((op)->flags & TIC80_OPERAND_SCALED) != 0) && ((insn) & (1 << 11))) argument 105 unsigned long insn, 112 if (M_SI (insn, operand) || M_LI (insn, operand)) 145 if (R_SCALED (insn, operan 186 print_one_instruction(struct disassemble_info *info, bfd_vma memaddr, unsigned long insn, const struct tic80_opcode *opcode) argument 257 print_instruction(struct disassemble_info *info, bfd_vma memaddr, unsigned long insn, const struct tic80_opcode *vec_opcode) argument 304 unsigned long insn; local [all...] |
/macosx-10.10.1/JavaScriptCore-7600.1.17/disassembler/udis86/ |
H A D | ud_opcode.py | 167 def parse(self, table, insn): 168 index = insn.opcodes[0]; 169 if insn.nByteInsn > 1: 172 index = insn.opcodes[1] 174 if insn.nByteInsn == 3: 176 index = insn.opcodes[2] 185 if ext in insn.opcext: 187 index = insn.opcext[ext] 190 if len(insn.vendor): 191 table = self.updateTable(table, index, 'vendor', insn [all...] |
/macosx-10.10.1/ruby-106/ruby/tool/ |
H A D | instruction.rb | 60 def add_optimized insn 61 @optimized << insn 134 @insns.each{|insn| 135 yield insn 165 def add_insn insn 166 @insns << insn 167 @insn_map[insn.name] = insn 217 body = insn = opes = pops = rets = nil 255 insn [all...] |
/macosx-10.10.1/tcl-105/tcl_ext/tcllib/tcllib/modules/page/ |
H A D | gen_peg_mecpu.tcl | 170 foreach insn $asmcode { 171 set i [lindex $insn 1] 175 foreach x [lrange $insn 1 end] { 204 foreach insn $asmcode { 205 foreach {label name} $insn break 206 if {$name eq ".C"} {lappend lines "" "-- [join [lrange $insn 2 end] " "]" ""} 213 incr pc [llength $insn] ; incr pc -1 226 set insn [lreplace $insn 2 2 "" '[lindex $insn [all...] |
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/MBlaze/Disassembler/ |
H A D | MBlazeDisassembler.cpp | 61 static unsigned getRD(uint32_t insn) { argument 62 if (!isMBlazeRegister((insn>>21)&0x1F)) 64 return getMBlazeRegisterFromNumbering((insn>>21)&0x1F); 67 static unsigned getRA(uint32_t insn) { argument 68 if (!getMBlazeRegisterFromNumbering((insn>>16)&0x1F)) 70 return getMBlazeRegisterFromNumbering((insn>>16)&0x1F); 73 static unsigned getRB(uint32_t insn) { argument 74 if (!getMBlazeRegisterFromNumbering((insn>>11)&0x1F)) 76 return getMBlazeRegisterFromNumbering((insn>>11)&0x1F); 79 static int64_t getRS(uint32_t insn) { argument 85 getIMM(uint32_t insn) argument 90 getSHT(uint32_t insn) argument 95 getFLAGS(int32_t insn) argument 99 getFSL(uint32_t insn) argument 104 decodeMUL(uint32_t insn) argument 114 decodeSEXT(uint32_t insn) argument 130 decodeBEQ(uint32_t insn) argument 148 decodeBEQI(uint32_t insn) argument 166 decodeBR(uint32_t insn) argument 179 decodeBRI(uint32_t insn) argument 199 decodeBSRL(uint32_t insn) argument 208 decodeBSRLI(uint32_t insn) argument 217 decodeRSUBK(uint32_t insn) argument 226 decodeFADD(uint32_t insn) argument 246 decodeGET(uint32_t insn) argument 300 decodeGETD(uint32_t insn) argument 354 decodeIDIV(uint32_t insn) argument 362 decodeLBU(uint32_t insn) argument 370 decodeLHU(uint32_t insn) argument 378 decodeLW(uint32_t insn) argument 387 decodeSB(uint32_t insn) argument 395 decodeSH(uint32_t insn) argument 403 decodeSW(uint32_t insn) argument 412 decodeMFS(uint32_t insn) argument 430 decodeOR(uint32_t insn) argument 438 decodeXOR(uint32_t insn) argument 446 decodeANDN(uint32_t insn) argument 454 decodeRTSD(uint32_t insn) argument 464 getOPCODE(uint32_t insn) argument 510 uint32_t insn; local [all...] |
/macosx-10.10.1/JavaScriptCore-7600.1.17/assembler/ |
H A D | MIPSAssembler.h | 733 MIPSWord* insn = reinterpret_cast<MIPSWord*>(reinterpret_cast<intptr_t>(code)); local 735 int32_t slotAddr = reinterpret_cast<int>(insn) + 4; 740 *insn = 0x3c000000 | (MIPSRegisters::t9 << OP_SH_RT) | ((toAddr >> 16) & 0xffff); 741 ++insn; 743 *insn = 0x34000000 | (MIPSRegisters::t9 << OP_SH_RT) | (MIPSRegisters::t9 << OP_SH_RS) | (toAddr & 0xffff); 744 ++insn; 746 *insn = 0x00000008 | (MIPSRegisters::t9 << OP_SH_RS); 747 ++insn; 751 *insn = 0x08000000 | ((toAddr & 0x0fffffff) >> 2); 752 ++insn; 764 MIPSWord* insn = reinterpret_cast<MIPSWord*>(reinterpret_cast<intptr_t>(m_buffer.data()) + from.m_offset); local 775 MIPSWord* insn = reinterpret_cast<MIPSWord*>(reinterpret_cast<intptr_t>(code) + from.m_offset); local 784 MIPSWord* insn = reinterpret_cast<MIPSWord*>(reinterpret_cast<intptr_t>(code) + from.m_offset); local 790 MIPSWord* insn = reinterpret_cast<MIPSWord*>(reinterpret_cast<intptr_t>(code) + from.m_offset); local 800 MIPSWord* insn = reinterpret_cast<MIPSWord*>(from); local 823 MIPSWord* insn = reinterpret_cast<MIPSWord*>(from); local 835 MIPSWord* insn = reinterpret_cast<MIPSWord*>(from); local 861 MIPSWord* insn = reinterpret_cast<MIPSWord*>(from); local 884 MIPSWord* insn = static_cast<MIPSWord*>(instructionStart); local 911 MIPSWord* insn = reinterpret_cast<MIPSWord*>(instructionStart); local 922 MIPSWord* insn = reinterpret_cast<MIPSWord*>(instructionStart); local 937 MIPSWord* insn = reinterpret_cast<MIPSWord*>(reinterpret_cast<intptr_t>(newBase) + pos); local 974 linkWithOffset(MIPSWord* insn, void* to) argument 1051 MIPSWord* insn = reinterpret_cast<MIPSWord*>(from); local [all...] |
/macosx-10.10.1/cxxfilt-11/cxxfilt/bfd/ |
H A D | elf32-or32.c | 62 unsigned long insn; local 67 insn = bfd_get_32 (abfd, (bfd_byte *) data + addr); 68 insn += symbol->section->output_section->vma; 69 insn += symbol->section->output_offset; 70 insn += symbol->value; 71 bfd_put_32 (abfd, insn, (bfd_byte *) data + addr); 90 unsigned short insn; local 95 insn = bfd_get_16 (abfd, (bfd_byte *) data + addr); 96 insn += symbol->section->output_section->vma; 97 insn 118 unsigned char insn; local 221 unsigned long insn; local 248 unsigned long insn, tmp; local 280 unsigned long insn, tmp; local [all...] |
H A D | xtensa-modules.c | 219 Field_t_Slot_inst_get (const xtensa_insnbuf insn) 222 tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); 227 Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 231 insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); 235 Field_s_Slot_inst_get (const xtensa_insnbuf insn) 238 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 243 Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 247 insn[0] = (insn[ 216 Field_t_Slot_inst_get(const xtensa_insnbuf insn) argument 224 Field_t_Slot_inst_set(xtensa_insnbuf insn, uint32 val) argument 232 Field_s_Slot_inst_get(const xtensa_insnbuf insn) argument 240 Field_s_Slot_inst_set(xtensa_insnbuf insn, uint32 val) argument 248 Field_r_Slot_inst_get(const xtensa_insnbuf insn) argument 256 Field_r_Slot_inst_set(xtensa_insnbuf insn, uint32 val) argument 264 Field_op2_Slot_inst_get(const xtensa_insnbuf insn) argument 272 Field_op2_Slot_inst_set(xtensa_insnbuf insn, uint32 val) argument 280 Field_op1_Slot_inst_get(const xtensa_insnbuf insn) argument 288 Field_op1_Slot_inst_set(xtensa_insnbuf insn, uint32 val) argument 296 Field_op0_Slot_inst_get(const xtensa_insnbuf insn) argument 304 Field_op0_Slot_inst_set(xtensa_insnbuf insn, uint32 val) argument 312 Field_n_Slot_inst_get(const xtensa_insnbuf insn) argument 320 Field_n_Slot_inst_set(xtensa_insnbuf insn, uint32 val) argument 328 Field_m_Slot_inst_get(const xtensa_insnbuf insn) argument 336 Field_m_Slot_inst_set(xtensa_insnbuf insn, uint32 val) argument 344 Field_sr_Slot_inst_get(const xtensa_insnbuf insn) argument 353 Field_sr_Slot_inst_set(xtensa_insnbuf insn, uint32 val) argument 363 Field_thi3_Slot_inst_get(const xtensa_insnbuf insn) argument 371 Field_thi3_Slot_inst_set(xtensa_insnbuf insn, uint32 val) argument 379 Field_op0_Slot_inst16a_get(const xtensa_insnbuf insn) argument 387 Field_op0_Slot_inst16a_set(xtensa_insnbuf insn, uint32 val) argument 395 Field_t_Slot_inst16b_get(const xtensa_insnbuf insn) argument 403 Field_t_Slot_inst16b_set(xtensa_insnbuf insn, uint32 val) argument 411 Field_r_Slot_inst16b_get(const xtensa_insnbuf insn) argument 419 Field_r_Slot_inst16b_set(xtensa_insnbuf insn, uint32 val) argument 427 Field_op0_Slot_inst16b_get(const xtensa_insnbuf insn) argument 435 Field_op0_Slot_inst16b_set(xtensa_insnbuf insn, uint32 val) argument 443 Field_z_Slot_inst16b_get(const xtensa_insnbuf insn) argument 451 Field_z_Slot_inst16b_set(xtensa_insnbuf insn, uint32 val) argument 459 Field_i_Slot_inst16b_get(const xtensa_insnbuf insn) argument 467 Field_i_Slot_inst16b_set(xtensa_insnbuf insn, uint32 val) argument 475 Field_s_Slot_inst16b_get(const xtensa_insnbuf insn) argument 483 Field_s_Slot_inst16b_set(xtensa_insnbuf insn, uint32 val) argument 491 Field_t_Slot_inst16a_get(const xtensa_insnbuf insn) argument 499 Field_t_Slot_inst16a_set(xtensa_insnbuf insn, uint32 val) argument 507 Field_bbi4_Slot_inst_get(const xtensa_insnbuf insn) argument 515 Field_bbi4_Slot_inst_set(xtensa_insnbuf insn, uint32 val) argument 523 Field_bbi_Slot_inst_get(const xtensa_insnbuf insn) argument 532 Field_bbi_Slot_inst_set(xtensa_insnbuf insn, uint32 val) argument 542 Field_imm12_Slot_inst_get(const xtensa_insnbuf insn) argument 550 Field_imm12_Slot_inst_set(xtensa_insnbuf insn, uint32 val) argument 558 Field_imm8_Slot_inst_get(const xtensa_insnbuf insn) argument 566 Field_imm8_Slot_inst_set(xtensa_insnbuf insn, uint32 val) argument 574 Field_s_Slot_inst16a_get(const xtensa_insnbuf insn) argument 582 Field_s_Slot_inst16a_set(xtensa_insnbuf insn, uint32 val) argument 590 Field_imm12b_Slot_inst_get(const xtensa_insnbuf insn) argument 599 Field_imm12b_Slot_inst_set(xtensa_insnbuf insn, uint32 val) argument 609 Field_imm16_Slot_inst_get(const xtensa_insnbuf insn) argument 617 Field_imm16_Slot_inst_set(xtensa_insnbuf insn, uint32 val) argument 625 Field_offset_Slot_inst_get(const xtensa_insnbuf insn) argument 633 Field_offset_Slot_inst_set(xtensa_insnbuf insn, uint32 val) argument 641 Field_r_Slot_inst16a_get(const xtensa_insnbuf insn) argument 649 Field_r_Slot_inst16a_set(xtensa_insnbuf insn, uint32 val) argument 657 Field_sa4_Slot_inst_get(const xtensa_insnbuf insn) argument 665 Field_sa4_Slot_inst_set(xtensa_insnbuf insn, uint32 val) argument 673 Field_sae4_Slot_inst_get(const xtensa_insnbuf insn) argument 681 Field_sae4_Slot_inst_set(xtensa_insnbuf insn, uint32 val) argument 689 Field_sae_Slot_inst_get(const xtensa_insnbuf insn) argument 698 Field_sae_Slot_inst_set(xtensa_insnbuf insn, uint32 val) argument 708 Field_sal_Slot_inst_get(const xtensa_insnbuf insn) argument 717 Field_sal_Slot_inst_set(xtensa_insnbuf insn, uint32 val) argument 727 Field_sargt_Slot_inst_get(const xtensa_insnbuf insn) argument 736 Field_sargt_Slot_inst_set(xtensa_insnbuf insn, uint32 val) argument 746 Field_sas4_Slot_inst_get(const xtensa_insnbuf insn) argument 754 Field_sas4_Slot_inst_set(xtensa_insnbuf insn, uint32 val) argument 762 Field_sas_Slot_inst_get(const xtensa_insnbuf insn) argument 771 Field_sas_Slot_inst_set(xtensa_insnbuf insn, uint32 val) argument 781 Field_sr_Slot_inst16a_get(const xtensa_insnbuf insn) argument 790 Field_sr_Slot_inst16a_set(xtensa_insnbuf insn, uint32 val) argument 800 Field_sr_Slot_inst16b_get(const xtensa_insnbuf insn) argument 809 Field_sr_Slot_inst16b_set(xtensa_insnbuf insn, uint32 val) argument 819 Field_st_Slot_inst_get(const xtensa_insnbuf insn) argument 828 Field_st_Slot_inst_set(xtensa_insnbuf insn, uint32 val) argument 838 Field_st_Slot_inst16a_get(const xtensa_insnbuf insn) argument 847 Field_st_Slot_inst16a_set(xtensa_insnbuf insn, uint32 val) argument 857 Field_st_Slot_inst16b_get(const xtensa_insnbuf insn) argument 866 Field_st_Slot_inst16b_set(xtensa_insnbuf insn, uint32 val) argument 876 Field_imm4_Slot_inst_get(const xtensa_insnbuf insn) argument 884 Field_imm4_Slot_inst_set(xtensa_insnbuf insn, uint32 val) argument 892 Field_imm4_Slot_inst16a_get(const xtensa_insnbuf insn) argument 900 Field_imm4_Slot_inst16a_set(xtensa_insnbuf insn, uint32 val) argument 908 Field_imm4_Slot_inst16b_get(const xtensa_insnbuf insn) argument 916 Field_imm4_Slot_inst16b_set(xtensa_insnbuf insn, uint32 val) argument 924 Field_mn_Slot_inst_get(const xtensa_insnbuf insn) argument 933 Field_mn_Slot_inst_set(xtensa_insnbuf insn, uint32 val) argument 943 Field_i_Slot_inst16a_get(const xtensa_insnbuf insn) argument 951 Field_i_Slot_inst16a_set(xtensa_insnbuf insn, uint32 val) argument 959 Field_imm6lo_Slot_inst16a_get(const xtensa_insnbuf insn) argument 967 Field_imm6lo_Slot_inst16a_set(xtensa_insnbuf insn, uint32 val) argument 975 Field_imm6lo_Slot_inst16b_get(const xtensa_insnbuf insn) argument 983 Field_imm6lo_Slot_inst16b_set(xtensa_insnbuf insn, uint32 val) argument 991 Field_imm6hi_Slot_inst16a_get(const xtensa_insnbuf insn) argument 999 Field_imm6hi_Slot_inst16a_set(xtensa_insnbuf insn, uint32 val) argument 1007 Field_imm6hi_Slot_inst16b_get(const xtensa_insnbuf insn) argument 1015 Field_imm6hi_Slot_inst16b_set(xtensa_insnbuf insn, uint32 val) argument 1023 Field_imm7lo_Slot_inst16a_get(const xtensa_insnbuf insn) argument 1031 Field_imm7lo_Slot_inst16a_set(xtensa_insnbuf insn, uint32 val) argument 1039 Field_imm7lo_Slot_inst16b_get(const xtensa_insnbuf insn) argument 1047 Field_imm7lo_Slot_inst16b_set(xtensa_insnbuf insn, uint32 val) argument 1055 Field_imm7hi_Slot_inst16a_get(const xtensa_insnbuf insn) argument 1063 Field_imm7hi_Slot_inst16a_set(xtensa_insnbuf insn, uint32 val) argument 1071 Field_imm7hi_Slot_inst16b_get(const xtensa_insnbuf insn) argument 1079 Field_imm7hi_Slot_inst16b_set(xtensa_insnbuf insn, uint32 val) argument 1087 Field_z_Slot_inst16a_get(const xtensa_insnbuf insn) argument 1095 Field_z_Slot_inst16a_set(xtensa_insnbuf insn, uint32 val) argument 1103 Field_imm6_Slot_inst16a_get(const xtensa_insnbuf insn) argument 1112 Field_imm6_Slot_inst16a_set(xtensa_insnbuf insn, uint32 val) argument 1122 Field_imm6_Slot_inst16b_get(const xtensa_insnbuf insn) argument 1131 Field_imm6_Slot_inst16b_set(xtensa_insnbuf insn, uint32 val) argument 1141 Field_imm7_Slot_inst16a_get(const xtensa_insnbuf insn) argument 1150 Field_imm7_Slot_inst16a_set(xtensa_insnbuf insn, uint32 val) argument 1160 Field_imm7_Slot_inst16b_get(const xtensa_insnbuf insn) argument 1169 Field_imm7_Slot_inst16b_set(xtensa_insnbuf insn, uint32 val) argument 8609 Slot_inst_decode(const xtensa_insnbuf insn) argument 9367 Slot_inst16b_decode(const xtensa_insnbuf insn) argument 9418 Slot_inst16a_decode(const xtensa_insnbuf insn) argument 9438 Slot_x24_Format_inst_0_get(const xtensa_insnbuf insn, xtensa_insnbuf slotbuf) argument 9445 Slot_x24_Format_inst_0_set(xtensa_insnbuf insn, const xtensa_insnbuf slotbuf) argument 9452 Slot_x16a_Format_inst16a_0_get(const xtensa_insnbuf insn, xtensa_insnbuf slotbuf) argument 9459 Slot_x16a_Format_inst16a_0_set(xtensa_insnbuf insn, const xtensa_insnbuf slotbuf) argument 9466 Slot_x16b_Format_inst16b_0_get(const xtensa_insnbuf insn, xtensa_insnbuf slotbuf) argument 9473 Slot_x16b_Format_inst16b_0_set(xtensa_insnbuf insn, const xtensa_insnbuf slotbuf) argument 9756 Format_x24_encode(xtensa_insnbuf insn) argument 9762 Format_x16a_encode(xtensa_insnbuf insn) argument 9768 Format_x16b_encode(xtensa_insnbuf insn) argument 9787 format_decoder(const xtensa_insnbuf insn) argument 9818 length_decoder(const unsigned char *insn) argument [all...] |
H A D | elf32-pj.c | 40 unsigned long insn; local 69 insn = bfd_get_32 (abfd, hit_data); 70 insn += sym_value + reloc_entry->addend; 71 bfd_put_32 (abfd, (bfd_vma) insn, hit_data); 78 insn = bfd_getb32 (hit_data); 79 insn += sym_value + reloc_entry->addend; 80 bfd_putb32 ((bfd_vma) insn, hit_data); 84 insn = bfd_getb16 (hit_data); 85 insn += sym_value + reloc_entry->addend 88 bfd_putb16 ((bfd_vma) insn, hit_dat [all...] |