/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/X86/InstPrinter/ |
H A D | X86InstComments.cpp | 37 Src1Name = getRegName(MI->getOperand(0).getReg()); 38 Src2Name = getRegName(MI->getOperand(2).getReg()); 39 DecodeINSERTPSMask(MI->getOperand(3).getImm(), ShuffleMask); 42 DestName = getRegName(MI->getOperand(0).getReg()); 43 Src1Name = getRegName(MI->getOperand(1).getReg()); 44 Src2Name = getRegName(MI->getOperand(2).getReg()); 45 DecodeINSERTPSMask(MI->getOperand(3).getImm(), ShuffleMask); 49 Src2Name = getRegName(MI->getOperand(2).getReg()); 50 Src1Name = getRegName(MI->getOperand(0).getReg()); 54 Src2Name = getRegName(MI->getOperand( [all...] |
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/Mips/ |
H A D | MipsDirectObjLower.cpp | 26 assert(Inst.getOperand(2).isImm()); 30 Shift = Inst.getOperand(2).getImm(); 37 (Inst.getOperand(2)).setImm(Shift); 67 assert(InstIn.getOperand(2).isImm()); 68 int64_t pos = InstIn.getOperand(2).getImm(); 69 assert(InstIn.getOperand(3).isImm()); 70 int64_t size = InstIn.getOperand(3).getImm(); 76 InstIn.getOperand(2).setImm(pos - 32); 82 InstIn.getOperand(3).setImm(size - 32);
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/macosx-10.10.1/llvmCore-3425.0.34/unittests/VMCore/ |
H A D | MDBuilderTest.cpp | 39 Value *Op = MD1->getOperand(0); 53 EXPECT_TRUE(isa<ConstantInt>(R1->getOperand(0))); 54 EXPECT_TRUE(isa<ConstantInt>(R1->getOperand(1))); 55 ConstantInt *C0 = cast<ConstantInt>(R1->getOperand(0)); 56 ConstantInt *C1 = cast<ConstantInt>(R1->getOperand(1)); 67 EXPECT_EQ(R0->getOperand(0), R0); 68 EXPECT_EQ(R1->getOperand(0), R1); 69 EXPECT_TRUE(R0->getNumOperands() == 1 || R0->getOperand(1) == 0); 70 EXPECT_TRUE(R1->getNumOperands() == 1 || R1->getOperand(1) == 0); 78 EXPECT_TRUE(isa<MDString>(R0->getOperand( [all...] |
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/XCore/ |
H A D | XCoreISelDAGToDAG.cpp | 101 if ((FIN = dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) 102 && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) 116 Base = Addr.getOperand(0); 122 if ((Addr.getOperand(0).getOpcode() == XCoreISD::DPRelativeWrapper) 123 && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) 126 Base = Addr.getOperand(0).getOperand(0); 137 Base = Addr.getOperand(0); 143 if ((Addr.getOperand(0).getOpcode() == XCoreISD::CPRelativeWrapper) 144 && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand( [all...] |
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/ARM/InstPrinter/ |
H A D | ARMInstPrinter.cpp | 73 switch (MI->getOperand(0).getImm()) { 95 const MCOperand &Dst = MI->getOperand(0); 96 const MCOperand &MO1 = MI->getOperand(1); 97 const MCOperand &MO2 = MI->getOperand(2); 98 const MCOperand &MO3 = MI->getOperand(3); 115 const MCOperand &Dst = MI->getOperand(0); 116 const MCOperand &MO1 = MI->getOperand(1); 117 const MCOperand &MO2 = MI->getOperand(2); 139 MI->getOperand(0).getReg() == ARM::SP && 151 if (Opcode == ARM::STR_PRE_IMM && MI->getOperand( [all...] |
/macosx-10.10.1/llvmCore-3425.0.34/lib/VMCore/ |
H A D | IntrinsicInst.cpp | 37 return CE->getOperand(0); 58 return MD->getOperand(0); 68 return cast<MDNode>(getArgOperand(0))->getOperand(0); 72 return cast<MDNode>(getArgOperand(0))->getOperand(0);
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/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/Hexagon/ |
H A D | HexagonSplitTFRCondSets.cpp | 89 int DestReg = MI->getOperand(0).getReg(); 90 int SrcReg1 = MI->getOperand(2).getReg(); 91 int SrcReg2 = MI->getOperand(3).getReg(); 107 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg1); 111 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg2); 119 int DestReg = MI->getOperand(0).getReg(); 120 int SrcReg1 = MI->getOperand(2).getReg(); 127 addReg(MI->getOperand(1).getReg()).addReg(SrcReg1); 132 addReg(MI->getOperand(1).getReg()). 133 addImm(MI->getOperand( [all...] |
H A D | HexagonAsmPrinter.h | 71 int value = MI->getOperand(OpNo).getImm(); 77 int value = MI->getOperand(OpNo).getImm(); 83 const MachineOperand &MO1 = MI->getOperand(OpNo); 84 const MachineOperand &MO2 = MI->getOperand(OpNo+1); 93 const MachineOperand &MO1 = MI->getOperand(OpNo); 94 const MachineOperand &MO2 = MI->getOperand(OpNo+1); 105 if (MI->getOperand(OpNo).isImm()) { 106 O << "$+" << MI->getOperand(OpNo).getImm()*4; 108 printOp(MI->getOperand(OpNo), O); 122 if (MI->getOperand(OpN [all...] |
H A D | HexagonPeephole.cpp | 131 MachineOperand &Dst = MI->getOperand(0); 132 MachineOperand &Src = MI->getOperand(1); 152 MachineOperand &Dst = MI->getOperand(0); 153 MachineOperand &Src1 = MI->getOperand(1); 154 MachineOperand &Src2 = MI->getOperand(2); 167 MachineOperand &Dst = MI->getOperand(0); 168 MachineOperand &Src = MI->getOperand(1); 185 MachineOperand &Dst = MI->getOperand(0); 186 MachineOperand &Src = MI->getOperand(1); 224 MachineOperand &Op0 = MI->getOperand( [all...] |
H A D | HexagonNewValueJump.cpp | 133 if (II->getOperand(i).isReg() && 134 (II->getOperand(i).isUse() || II->getOperand(i).isDef())) { 137 unsigned Reg = II->getOperand(i).getReg(); 212 int64_t v = MI->getOperand(2).getImm(); 226 cmpReg1 = MI->getOperand(1).getReg(); 229 cmpOp2 = MI->getOperand(2).getReg(); 408 predReg = MI->getOperand(0).getReg(); 413 // if(!jmpInstr->getOperand(0).isKill()) break; 437 jmpTarget = MI->getOperand( [all...] |
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/PowerPC/InstPrinter/ |
H A D | PPCInstPrinter.cpp | 34 unsigned char SH = MI->getOperand(2).getImm(); 35 unsigned char MB = MI->getOperand(3).getImm(); 36 unsigned char ME = MI->getOperand(4).getImm(); 57 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) { 67 unsigned char SH = MI->getOperand(2).getImm(); 68 unsigned char ME = MI->getOperand(3).getImm(); 89 unsigned Code = MI->getOperand(OpNo).getImm(); 91 unsigned CCReg = MI->getOperand(OpNo+1).getReg(); 139 char Value = MI->getOperand(OpN [all...] |
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/CellSPU/ |
H A D | SPUAsmPrinter.cpp | 64 const MachineOperand &MO = MI->getOperand(OpNo); 85 unsigned int value = MI->getOperand(OpNo).getImm(); 93 char value = MI->getOperand(OpNo).getImm(); 103 O << (short) MI->getOperand(OpNo).getImm(); 109 O << (unsigned short)MI->getOperand(OpNo).getImm(); 117 const MachineOperand &MO = MI->getOperand(OpNo); 125 unsigned int value = MI->getOperand(OpNo).getImm(); 133 short value = MI->getOperand(OpNo).getImm(); 142 short value = MI->getOperand(OpNo).getImm(); 150 assert(MI->getOperand(OpN [all...] |
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/Sparc/ |
H A D | SparcISelDAGToDAG.cpp | 85 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) { 88 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) { 92 Base = Addr.getOperand(0); 98 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) { 99 Base = Addr.getOperand(1); 100 Offset = Addr.getOperand(0).getOperand(0); 103 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) { 104 Base = Addr.getOperand(0); 105 Offset = Addr.getOperand( [all...] |
/macosx-10.10.1/llvmCore-3425.0.34/lib/Transforms/InstCombine/ |
H A D | InstCombineVectorOps.cpp | 38 isa<ConstantInt>(I->getOperand(2))) 44 (CheapToScalarize(BO->getOperand(0), isConstant) || 45 CheapToScalarize(BO->getOperand(1), isConstant))) 49 (CheapToScalarize(CI->getOperand(0), isConstant) || 50 CheapToScalarize(CI->getOperand(1), isConstant))) 71 if (!isa<ConstantInt>(III->getOperand(2))) 73 unsigned IIElt = cast<ConstantInt>(III->getOperand(2))->getZExtValue(); 78 return III->getOperand(1); 82 return FindScalarElement(III->getOperand(0), EltNo); 86 unsigned LHSWidth = SVI->getOperand( [all...] |
H A D | InstCombineSelect.cpp | 32 LHS = ICI->getOperand(0); 33 RHS = ICI->getOperand(1); 36 if (SI->getTrueValue() == ICI->getOperand(0) && 37 SI->getFalseValue() == ICI->getOperand(1)) { 52 if (SI->getTrueValue() == ICI->getOperand(1) && 53 SI->getFalseValue() == ICI->getOperand(0)) { 130 if (TI->getOperand(0)->getType() != FI->getOperand(0)->getType()) 136 FI->getOperand(0)->getType()->getVectorNumElements()) 143 Value *NewSI = Builder->CreateSelect(SI.getCondition(), TI->getOperand( [all...] |
H A D | InstCombineCasts.cpp | 43 if (ConstantInt *RHS = dyn_cast<ConstantInt>(I->getOperand(1))) { 48 return I->getOperand(0); 55 return I->getOperand(0); 63 DecomposeSimpleLinearExpr(I->getOperand(0), SubScale, Offset); 112 DecomposeSimpleLinearExpr(AI.getOperand(0), ArraySizeScale, ArrayOffset); 180 Value *LHS = EvaluateInDifferentType(I->getOperand(0), Ty, isSigned); 181 Value *RHS = EvaluateInDifferentType(I->getOperand(1), Ty, isSigned); 191 if (I->getOperand(0)->getType() == Ty) 192 return I->getOperand(0); 196 Res = CastInst::CreateIntegerCast(I->getOperand( [all...] |
H A D | InstCombineAndOrXor.cpp | 135 Value *X = Op->getOperand(0); 259 Value *ShVal = Op->getOperand(0); 349 !isa<ConstantInt>(LHSI->getOperand(1))) return 0; 351 ConstantInt *N = cast<ConstantInt>(LHSI->getOperand(1)); 386 return Builder->CreateSub(LHSI->getOperand(0), RHS, "fold"); 387 return Builder->CreateAdd(LHSI->getOperand(0), RHS, "fold"); 505 if (ConstantInt *C = dyn_cast<ConstantInt>(I->getOperand(1))) 507 X = I->getOperand(0); 517 if (ConstantInt *C = dyn_cast<ConstantInt>(I->getOperand(1))) 519 X = I->getOperand( [all...] |
H A D | InstCombineShifts.cpp | 23 assert(I.getOperand(1)->getType() == I.getOperand(0)->getType()); 24 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); 92 if (MaskedValueIsZero(I->getOperand(0), 95 return CanEvaluateTruncated(I->getOperand(0), Ty); 112 return CanEvaluateShifted(I->getOperand(0), NumBits, isLeftShift, IC) && 113 CanEvaluateShifted(I->getOperand(1), NumBits, isLeftShift, IC); 117 CI = dyn_cast<ConstantInt>(I->getOperand(1)); 132 if (MaskedValueIsZero(I->getOperand( [all...] |
/macosx-10.10.1/llvmCore-3425.0.34/lib/CodeGen/ |
H A D | AntiDepBreaker.h | 64 if (MI && MI->getOperand(0).isReg() && MI->getOperand(0).getReg() == OldReg) 65 MI->getOperand(0).setReg(NewReg);
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H A D | ExpandPostRAPseudos.cpp | 88 MachineOperand &MO = MI->getOperand(i); 97 assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) && 98 MI->getOperand(1).isImm() && 99 (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) && 100 MI->getOperand(3).isImm() && "Invalid subreg_to_reg"); 102 unsigned DstReg = MI->getOperand(0).getReg(); 103 unsigned InsReg = MI->getOperand(2).getReg(); 104 assert(!MI->getOperand( [all...] |
/macosx-10.10.1/llvmCore-3425.0.34/lib/MC/MCDisassembler/ |
H A D | EDOperand.cpp | 142 result = Inst.Inst->getOperand(MCOpIndex).getImm(); 146 unsigned reg = Inst.Inst->getOperand(MCOpIndex).getReg(); 151 int64_t displacement = Inst.Inst->getOperand(MCOpIndex).getImm(); 166 unsigned baseReg = Inst.Inst->getOperand(MCOpIndex).getReg(); 167 uint64_t scaleAmount = Inst.Inst->getOperand(MCOpIndex+1).getImm(); 168 unsigned indexReg = Inst.Inst->getOperand(MCOpIndex+2).getReg(); 169 int64_t displacement = Inst.Inst->getOperand(MCOpIndex+3).getImm(); 173 unsigned segmentReg = Inst.Inst->getOperand(MCOpIndex+4).getReg(); 213 if (!Inst.Inst->getOperand(MCOpIndex).isImm()) 216 result = Inst.Inst->getOperand(MCOpInde [all...] |
/macosx-10.10.1/llvmCore-3425.0.34/lib/MC/ |
H A D | MCInstrAnalysis.cpp | 19 int64_t Imm = Inst.getOperand(0).getImm();
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/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/MSP430/InstPrinter/ |
H A D | MSP430InstPrinter.cpp | 36 const MCOperand &Op = MI->getOperand(OpNo); 48 const MCOperand &Op = MI->getOperand(OpNo); 62 const MCOperand &Base = MI->getOperand(OpNo); 63 const MCOperand &Disp = MI->getOperand(OpNo+1); 90 unsigned CC = MI->getOperand(OpNo).getImm();
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/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/ARM/ |
H A D | ARMExpandPseudoInsts.cpp | 78 const MachineOperand &MO = OldMI.getOperand(i); 387 bool DstIsDead = MI.getOperand(OpIdx).isDead(); 388 unsigned DstReg = MI.getOperand(OpIdx++).getReg(); 400 MIB.addOperand(MI.getOperand(OpIdx++)); 403 MIB.addOperand(MI.getOperand(OpIdx++)); 404 MIB.addOperand(MI.getOperand(OpIdx++)); 407 MIB.addOperand(MI.getOperand(OpIdx++)); 417 MIB.addOperand(MI.getOperand(OpIdx++)); 418 MIB.addOperand(MI.getOperand(OpIdx++)); 423 MachineOperand MO = MI.getOperand(SrcOpId [all...] |
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/MSP430/ |
H A D | MSP430ISelDAGToDAG.cpp | 145 SDValue N0 = N.getOperand(0); 211 if (!MatchAddress(N.getNode()->getOperand(0), AM) && 212 !MatchAddress(N.getNode()->getOperand(1), AM)) 215 if (!MatchAddress(N.getNode()->getOperand(1), AM) && 216 !MatchAddress(N.getNode()->getOperand(0), AM)) 225 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 229 if (!MatchAddress(N.getOperand(0), AM) && 233 CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getAPIntValue())) { 421 Node->getOperand(0), Node->getOperand( [all...] |