/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/CellSPU/ |
H A D | SPUInstrInfo.cpp | 371 MIB.addMBB(TBB); 380 MIB.addMBB(TBB); 385 MIB.addReg(Cond[1].getReg()).addMBB(TBB); 390 MIB.addMBB(TBB); 402 MIB.addReg(Cond[1].getReg()).addMBB(TBB); 403 MIB2.addMBB(FBB); 408 MIB.addMBB(FBB);
|
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/Sparc/ |
H A D | SparcInstrInfo.cpp | 206 .addMBB(UnCondBrIter->getOperand(0).getMBB()).addImm(BranchCode); 208 .addMBB(TargetBB); 240 BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB); 248 BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC); 250 BuildMI(&MBB, DL, get(SP::FBCOND)).addMBB(TBB).addImm(CC); 254 BuildMI(&MBB, DL, get(SP::BA)).addMBB(FBB);
|
H A D | SparcISelLowering.cpp | 1221 BuildMI(BB, dl, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC); 1236 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) 1237 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
|
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/MBlaze/ |
H A D | MBlazeInstrInfo.cpp | 202 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB); 204 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()).addMBB(TBB); 208 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()).addMBB(TBB); 209 BuildMI(&MBB, DL, get(MBlaze::BRID)).addMBB(FBB);
|
H A D | MBlazeISelLowering.cpp | 306 .addMBB(finish); 311 .addReg(IVAL).addMBB(MBB) 312 .addReg(NDST).addMBB(loop); 317 .addReg(IAMT).addMBB(MBB) 318 .addReg(NAMT).addMBB(loop); 335 .addMBB(loop); 339 .addReg(IVAL).addMBB(MBB) 340 .addReg(NDST).addMBB(loop); 397 .addMBB(dneBB); 403 // .addReg(MI->getOperand(1).getReg()).addMBB(flsB [all...] |
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/XCore/ |
H A D | XCoreInstrInfo.cpp | 287 BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(TBB); 292 .addMBB(TBB); 301 .addMBB(TBB); 302 BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(FBB);
|
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/Mips/ |
H A D | MipsInstrInfo.cpp | 189 MIB.addMBB(TBB); 211 BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(FBB); 218 BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(TBB);
|
H A D | MipsLongBranch.cpp | 236 MIB.addMBB(MBBOpnd); 286 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::BAL_BR)).addMBB(BalTgtMBB); 338 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::BAL_BR)).addMBB(BalTgtMBB); 362 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::J)).addMBB(TgtMBB);
|
H A D | MipsISelLowering.cpp | 948 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB); 951 .addReg(Mips::ZERO).addMBB(sinkMBB); 969 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB) 970 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB); 974 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB) 975 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB); 1023 BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB); 1029 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink); 1039 .addReg(VR2).addMBB(FBB).addReg(VR1).addMBB(TB [all...] |
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/MSP430/ |
H A D | MSP430InstrInfo.cpp | 272 BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(TBB); 278 BuildMI(&MBB, DL, get(MSP430::JCC)).addMBB(TBB).addImm(Cond[0].getImm()); 283 BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(FBB);
|
H A D | MSP430BranchSelector.cpp | 161 I = BuildMI(MBB, I, dl, TII->get(MSP430::Bi)).addMBB(Dest);
|
H A D | MSP430ISelLowering.cpp | 1093 .addMBB(RemBB) 1102 .addReg(SrcReg).addMBB(BB) 1103 .addReg(ShiftReg2).addMBB(LoopBB); 1105 .addReg(ShiftAmtSrcReg).addMBB(BB) 1106 .addReg(ShiftAmtReg2).addMBB(LoopBB); 1112 .addMBB(LoopBB) 1118 .addReg(SrcReg).addMBB(BB) 1119 .addReg(ShiftReg2).addMBB(LoopBB); 1172 .addMBB(copy1MBB) 1189 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MB [all...] |
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/NVPTX/ |
H A D | NVPTXInstrInfo.cpp | 314 BuildMI(&MBB, DL, get(NVPTX::GOTO)).addMBB(TBB); 317 .addReg(Cond[0].getReg()).addMBB(TBB); 323 .addReg(Cond[0].getReg()).addMBB(TBB); 324 BuildMI(&MBB, DL, get(NVPTX::GOTO)).addMBB(FBB);
|
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/Hexagon/ |
H A D | HexagonHardwareLoops.cpp | 499 TII->get(Hexagon::LOOP0_r)).addMBB(LoopStart).addReg(CountReg); 505 TII->get(Hexagon::LOOP0_i)).addMBB(LoopStart).addImm(CountImm); 518 BuildMI(*LastMBB, LastI, dl, TII->get(Hexagon::ENDLOOP0)).addMBB(LoopStart); 645 .addMBB(MII->getOperand(0).getMBB());
|
H A D | HexagonNewValueJump.cpp | 614 .addMBB(jmpTarget); 621 .addMBB(jmpTarget);
|
H A D | HexagonInstrInfo.cpp | 152 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB); 155 get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB); 160 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB); 161 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
|
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/PowerPC/ |
H A D | PPCBranchSelector.cpp | 167 I = BuildMI(MBB, I, dl, TII->get(PPC::B)).addMBB(Dest);
|
H A D | PPCInstrInfo.cpp | 390 BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB); 394 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB); 397 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); 405 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB); 408 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); 409 BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
|
H A D | PPCCTRLoops.cpp | 708 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(BranchTarget);
|
H A D | PPCISelLowering.cpp | 4927 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB); 5056 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB); 5142 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); 5158 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB) 5159 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 5270 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB); 5278 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB); 5279 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB); 5414 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB); 5426 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MB [all...] |
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/ARM/ |
H A D | ARMConstantIslandPass.cpp | 889 BuildMI(OrigBB, DebugLoc(), TII->get(Opc)).addMBB(NewBB); 891 BuildMI(OrigBB, DebugLoc(), TII->get(Opc)).addMBB(NewBB) 1259 BuildMI(UserMBB, DebugLoc(), TII->get(UncondBr)).addMBB(NewMBB); 1261 BuildMI(UserMBB, DebugLoc(), TII->get(UncondBr)).addMBB(NewMBB) 1633 .addMBB(NextBB).addImm(CC).addReg(CCReg); 1637 BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB) 1640 BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB); 1822 .addReg(Reg).addMBB(DestBB,Br.MI->getOperand(0).getTargetFlags()); 2048 BuildMI(NewBB, DebugLoc(), TII->get(ARM::t2B)).addMBB(BB)
|
H A D | ARMISelLowering.cpp | 5425 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR); 5441 .addMBB(loop1MBB).addImm(ARMCC::NE).addReg(ARM::CPSR); 5545 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR); 5663 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR); 5769 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR); 5800 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR); 6062 .addMBB(TrapBB) 6116 .addMBB(TrapBB) 6206 .addMBB(TrapBB) 6538 .addReg(varLoop).addMBB(loopMB [all...] |
/macosx-10.10.1/llvmCore-3425.0.34/include/llvm/CodeGen/ |
H A D | MachineInstrBuilder.h | 93 const MachineInstrBuilder &addMBB(MachineBasicBlock *MBB, function in class:llvm::MachineInstrBuilder
|
/macosx-10.10.1/llvmCore-3425.0.34/lib/CodeGen/ |
H A D | MachineSSAUpdater.cpp | 192 MIB.addReg(PredValues[i].second).addMBB(PredValues[i].first);
|
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/X86/ |
H A D | X86FastISel.cpp | 1098 .addMBB(TrueMBB); 1104 .addMBB(TrueMBB); 1138 .addMBB(TrueMBB); 1155 .addMBB(TrueMBB);
|