Searched refs:addImm (Results 1 - 25 of 71) sorted by relevance

123

/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/CellSPU/
H A DSPUInstrBuilder.h36 return MIB.addImm(Offset).addFrameIndex(FI);
38 return MIB.addFrameIndex(FI).addImm(Offset);
H A DSPUFrameLowering.cpp125 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R0).addImm(16)
129 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R1).addImm(FrameSize)
133 .addImm(FrameSize);
138 .addImm(-16)
141 .addImm(FrameSize);
150 .addImm(16);
210 .addImm(FrameSize + LinkSlotOffset)
214 .addImm(FrameSize);
219 .addImm(16)
222 .addImm(FrameSiz
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/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/PowerPC/
H A DPPCInstrBuilder.h36 return MIB.addImm(Offset).addFrameIndex(FI);
38 return MIB.addFrameIndex(FI).addImm(Offset);
H A DPPCBranchSelector.cpp153 .addImm(PPC::InvertPredicate(Pred)).addReg(CRReg).addImm(2);
155 BuildMI(MBB, I, dl, TII->get(PPC::BDZ)).addImm(2);
157 BuildMI(MBB, I, dl, TII->get(PPC::BDZ8)).addImm(2);
159 BuildMI(MBB, I, dl, TII->get(PPC::BDNZ)).addImm(2);
161 BuildMI(MBB, I, dl, TII->get(PPC::BDNZ8)).addImm(2);
H A DPPCFrameLowering.cpp139 .addImm(UsedRegMask);
143 .addImm(UsedRegMask);
148 .addImm(UsedRegMask >> 16);
152 .addImm(UsedRegMask >> 16);
157 .addImm(UsedRegMask >> 16);
161 .addImm(UsedRegMask >> 16);
165 .addImm(UsedRegMask & 0xFFFF);
334 .addImm(FPOffset/4)
340 .addImm(LROffset / 4)
351 .addImm(FPOffse
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H A DPPCRegisterInfo.cpp246 .addImm(CalleeAmt);
250 .addImm(CalleeAmt >> 16);
253 .addImm(CalleeAmt & 0xFFFF);
330 .addImm(FrameSize);
334 .addImm(0)
338 .addImm(0)
342 .addImm(0)
363 .addImm(maxCallFrameSize);
368 .addImm(maxCallFrameSize)
379 .addImm(maxCallFrameSiz
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/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/X86/
H A DX86InstrBuilder.h93 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0);
99 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0);
117 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1)
118 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0);
133 MIB.addImm(AM.Scale).addReg(AM.IndexReg);
137 MIB.addImm(AM.Disp);
177 return MIB.addReg(GlobalBaseReg).addImm(1).addReg(0)
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/Hexagon/
H A DHexagonExpandPredSpillCode.cpp91 HEXAGON_RESERVED_REG_1).addImm(Offset);
100 .addImm(0).addReg(HEXAGON_RESERVED_REG_2);
103 HEXAGON_RESERVED_REG_1).addReg(FP).addImm(Offset);
109 .addImm(0)
117 addReg(FP).addImm(Offset).addReg(HEXAGON_RESERVED_REG_2);
135 HEXAGON_RESERVED_REG_1).addImm(Offset);
143 .addImm(0);
148 HEXAGON_RESERVED_REG_1).addReg(FP).addImm(Offset);
152 .addImm(0);
158 HEXAGON_RESERVED_REG_2).addReg(FP).addImm(Offse
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H A DHexagonSplitTFRCondSets.cpp133 addImm(MI->getOperand(3).getImm());
154 addImm(MI->getOperand(2).getImm());
183 DestReg).addReg(SrcReg1).addImm(Immed1);
186 DestReg).addReg(SrcReg1).addImm(Immed2);
H A DHexagonRegisterInfo.cpp198 TII.get(Hexagon::CONST32_Int_Real), dstReg).addImm(Offset);
205 dstReg).addReg(FrameReg).addImm(Offset);
227 TII.get(Hexagon::CONST32_Int_Real), resReg).addImm(Offset);
234 resReg).addReg(FrameReg).addImm(Offset);
247 TII.get(Hexagon::CONST32_Int_Real), resReg).addImm(Offset);
256 resReg).addReg(FrameReg).addImm(Offset);
263 TII.get(Hexagon::CONST32_Int_Real), dstReg).addImm(Offset);
H A DHexagonFrameLowering.cpp149 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::ALLOCFRAME)).addImm(0);
153 HEXAGON_RESERVED_REG_1).addImm(NumBytes);
159 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::ALLOCFRAME)).addImm(NumBytes);
197 .addImm(NumBytes);
199 BuildMI(MBB, MBBI, dl, TII.get(Hexagon::DEALLOCFRAME)).addImm(NumBytes);
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/Sparc/
H A DSparcFrameLowering.cpp56 .addReg(SP::O6).addImm(NumBytes);
61 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
64 .addReg(SP::G1).addImm(NumBytes & ((1 << 10)-1));
H A DSparcInstrInfo.cpp122 .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
206 .addMBB(UnCondBrIter->getOperand(0).getMBB()).addImm(BranchCode);
248 BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC);
250 BuildMI(&MBB, DL, get(SP::FBCOND)).addMBB(TBB).addImm(CC);
307 BuildMI(MBB, I, DL, get(SP::STri)).addFrameIndex(FI).addImm(0)
310 BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0)
313 BuildMI(MBB, I, DL, get(SP::STDFri)).addFrameIndex(FI).addImm(0)
328 BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0);
330 BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(
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/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/XCore/
H A DXCoreRegisterInfo.cpp140 .addImm(Amount);
145 .addImm(Amount);
252 .addImm(Offset);
258 .addImm(Offset);
263 .addImm(Offset);
280 .addImm(Offset);
286 .addImm(Offset);
291 .addImm(Offset);
310 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg).addImm(Value);
H A DXCoreInstrInfo.cpp344 .addImm(0);
349 BuildMI(MBB, I, DL, get(XCore::LDAWSP_ru6), DestReg).addImm(0);
373 .addImm(0);
386 .addImm(0);
394 .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/ARM/
H A DThumb2RegisterInfo.cpp50 .addConstantPoolIndex(Idx).addImm((int64_t)ARMCC::AL).addReg(0)
H A DThumb1InstrInfo.cpp75 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
102 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
H A DARMExpandPseudoInsts.cpp558 MIB.addImm(Lane);
635 LO16 = LO16.addImm(SOImmValV1);
636 HI16 = HI16.addImm(SOImmValV2);
639 LO16.addImm(Pred).addReg(PredReg).addReg(0);
640 HI16.addImm(Pred).addReg(PredReg).addReg(0);
665 LO16 = LO16.addImm(Lo16);
666 HI16 = HI16.addImm(Hi16);
676 LO16.addImm(Pred).addReg(PredReg);
677 HI16.addImm(Pred).addReg(PredReg);
697 .addImm(M
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H A DThumb2InstrInfo.cpp144 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
170 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
194 .addImm(NumBytes)
195 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
201 .addImm(NumBytes >> 16)
202 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
211 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
217 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
242 .addReg(BaseReg).addImm(ThisVal/4).setMIFlags(MIFlags));
282 .addImm(ThisVa
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/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/Mips/
H A DMipsLongBranch.cpp283 .addReg(Mips::SP).addImm(-8);
285 .addReg(Mips::SP).addImm(0);
287 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LUi), Mips::AT).addImm(Hi)
293 .addReg(Mips::AT).addImm(Lo);
297 .addReg(Mips::SP).addImm(0);
300 .addReg(Mips::SP).addImm(8)->setIsInsideBundle();
327 .addReg(Mips::SP_64).addImm(-16);
329 .addReg(Mips::SP_64).addImm(0);
331 .addImm(Highest);
333 .addReg(Mips::AT_64).addImm(Highe
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H A DMips16FrameLowering.cpp43 BuildMI(MBB, MBBI, dl, TII.get(Mips::SaveRaF16)).addImm(StackSize);
61 BuildMI(MBB, MBBI, dl, TII.get(Mips::RestoreRaF16)).addImm(StackSize);
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/MBlaze/
H A DMBlazeFrameLowering.cpp256 .addFrameIndex(FI).addImm(0);
264 .addFrameIndex(R17FI).addImm(0);
267 .addFrameIndex(R18FI).addImm(0);
275 .addFrameIndex(MSRFI).addImm(0);
278 .addFrameIndex(MSRFI).addImm(0);
285 .addFrameIndex(R18FI).addImm(0);
288 .addFrameIndex(R17FI).addImm(0);
294 .addFrameIndex(VFI[--i]).addImm(0);
367 .addReg(MBlaze::R1).addImm(-StackSize);
372 .addReg(MBlaze::R15).addReg(MBlaze::R1).addImm(RAOffse
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/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/MSP430/
H A DMSP430RegisterInfo.cpp126 .addReg(MSP430::SPW).addImm(Amount);
135 .addReg(MSP430::SPW).addImm(Amount);
153 MSP430::SPW).addReg(MSP430::SPW).addImm(CalleeAmt);
211 .addReg(DstReg).addImm(-Offset);
214 .addReg(DstReg).addImm(Offset);
H A DMSP430InstrInfo.cpp52 .addFrameIndex(FrameIdx).addImm(0)
56 .addFrameIndex(FrameIdx).addImm(0)
80 .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO);
83 .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO);
278 BuildMI(&MBB, DL, get(MSP430::JCC)).addMBB(TBB).addImm(Cond[0].getImm());
/macosx-10.10.1/llvmCore-3425.0.34/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp561 .addImm(ExtraInfo);
625 .addReg(Reg, RegState::Debug).addImm(Offset)
642 .addReg(0U).addImm(DI->getOffset())
647 .addCImm(CI).addImm(DI->getOffset())
651 .addImm(CI->getZExtValue()).addImm(DI->getOffset())
655 .addFPImm(CF).addImm(DI->getOffset())
659 .addReg(Reg, RegState::Debug).addImm(DI->getOffset())
1247 .addImm(Imm);
1251 .addImm(Im
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