/macosx-10.10.1/llvmCore-3425.0.34/utils/TableGen/ |
H A D | TableGen.cpp | 95 bool operator()(raw_ostream &OS, RecordKeeper &Records) { argument 98 OS << Records; // No argument, dump all contents local 101 EmitCodeEmitter(Records, OS); 104 EmitRegisterInfo(Records, OS); 107 EmitInstrInfo(Records, OS); 110 EmitCallingConv(Records, OS); 113 EmitAsmWriter(Records, OS); 116 EmitAsmMatcher(Records, OS); 119 EmitDisassembler(Records, OS); 122 EmitPseudoLowering(Records, O [all...] |
H A D | DisassemblerEmitter.cpp | 106 void EmitDisassembler(RecordKeeper &Records, raw_ostream &OS) { argument 107 CodeGenTarget Target(Records); 133 EmitFixedLenDecoder(Records, OS, "ARM", 141 EmitFixedLenDecoder(Records, OS, Target.getName(),
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H A D | PseudoLoweringEmitter.cpp | 45 RecordKeeper &Records; member in class:__anon10638::PseudoLoweringEmitter 61 PseudoLoweringEmitter(RecordKeeper &R) : Records(R), Target(R) {} 269 Record *ExpansionClass = Records.getClass("PseudoInstExpansion"); 270 Record *InstructionClass = Records.getClass("Instruction"); 276 Records.getDefs().begin(), E = Records.getDefs().end(); I != E; ++I) {
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H A D | DFAPacketizerEmitter.cpp | 41 RecordKeeper &Records; member in class:__anon10615::DFAPacketizerEmitter 267 allInsnClasses(), Records(R) {} 350 Records.getAllDerivedDefinitions("ProcessorItineraries"); 404 Records.getAllDerivedDefinitions("ProcessorItineraries"); 421 Records.getAllDerivedDefinitions("InstrItinClass").size();
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H A D | CodeGenTarget.cpp | 124 : Records(records), RegBank(0), SchedModels(0) { 125 std::vector<Record*> Targets = Records.getAllDerivedDefinitions("Target"); 198 RegBank = new CodeGenRegBank(Records); 203 RegAltNameIndices = Records.getAllDerivedDefinitions("RegAltNameIndex"); 252 SchedModels = new CodeGenSchedModels(Records, *this); 257 std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction"); 269 RecordKeeper &Records) { 270 const Record *Rec = Records.getDef(Name); 316 const CodeGenInstruction *Instr = GetInstByName(*p, Insts, Records); 267 GetInstByName(const char *Name, const DenseMap<const Record*, CodeGenInstruction*> &Insts, RecordKeeper &Records) argument
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H A D | CodeGenTarget.h | 65 RecordKeeper &Records; member in class:llvm::CodeGenTarget 80 CodeGenTarget(RecordKeeper &Records);
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H A D | CodeEmitterGen.cpp | 38 RecordKeeper &Records; member in class:__anon10602::CodeEmitterGen 40 CodeEmitterGen(RecordKeeper &R) : Records(R) {} 234 CodeGenTarget Target(Records); 235 std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
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H A D | CallingConvEmitter.cpp | 23 RecordKeeper &Records; member in class:__anon10601::CallingConvEmitter 25 explicit CallingConvEmitter(RecordKeeper &R) : Records(R) {} 38 std::vector<Record*> CCs = Records.getAllDerivedDefinitions("CallingConv");
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H A D | InstrInfoEmitter.cpp | 31 RecordKeeper &Records; member in class:__anon10635::InstrInfoEmitter 37 Records(R), CDP(R), SchedModels(CDP.getTargetInfo().getSchedModels()) {} 388 CodeGenTarget Target(Records);
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H A D | SubtargetEmitter.cpp | 61 RecordKeeper &Records; member in class:__anon10642::SubtargetEmitter 102 Records(R), SchedModels(TGT.getSchedModels()), Target(TGT.getName()) {} 116 std::vector<Record*> DefList = Records.getAllDerivedDefinitions(ClassName); 175 Records.getAllDerivedDefinitions("SubtargetFeature"); 239 Records.getAllDerivedDefinitions("Processor"); 1134 Records.getAllDerivedDefinitions("Processor"); 1208 std::vector<Record*> Prologs = Records.getAllDerivedDefinitions("PredicateProlog"); 1289 Records.getAllDerivedDefinitions("SubtargetFeature");
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H A D | AsmWriterEmitter.cpp | 33 RecordKeeper &Records; member in class:__anon10600::AsmWriterEmitter 37 AsmWriterEmitter(RecordKeeper &R) : Records(R) {} 277 CodeGenTarget Target(Records); 594 CodeGenTarget Target(Records); 771 CodeGenTarget Target(Records); 784 Records.getAllDerivedDefinitions("InstAlias");
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H A D | CodeGenSchedule.cpp | 88 Records(RK), Target(TGT), NumItineraryClasses(0) { 137 RecVec ProcRecords = Records.getAllDerivedDefinitions("Processor"); 144 Record *NoModelDef = Records.getDef("NoSchedModel"); 145 Record *NoItinsDef = Records.getDef("NoItineraries"); 230 RecVec InstRWDefs = Records.getAllDerivedDefinitions("InstRW"); 245 RecVec ItinRWDefs = Records.getAllDerivedDefinitions("ItinRW"); 261 RecVec AliasDefs = Records.getAllDerivedDefinitions("SchedAlias"); 319 RecVec RWDefs = Records.getAllDerivedDefinitions("SchedReadWrite"); 538 RecVec InstRWDefs = Records.getAllDerivedDefinitions("InstRW"); 821 RecVec ItinRWDefs = Records [all...] |
H A D | AsmMatcherEmitter.cpp | 128 RecordKeeper &Records; member in class:__anon10596::AsmMatcherEmitter 130 AsmMatcherEmitter(RecordKeeper &R) : Records(R) {} 592 /// Tracked Records 593 RecordKeeper &Records; member in class:__anon10596::AsmMatcherInfo 652 RecordKeeper &Records); 671 return Records; 1173 Records.getAllDerivedDefinitions("AsmOperandClass"); 1243 : Records(records), AsmParser(asmParser), Target(target) { 1284 Records.getAllDerivedDefinitions("Predicate"); 1366 Records [all...] |
H A D | IntrinsicEmitter.cpp | 26 RecordKeeper &Records; member in class:__anon10636::IntrinsicEmitter 32 : Records(R), TargetOnly(T) {} 68 std::vector<CodeGenIntrinsic> Ints = LoadIntrinsics(Records, TargetOnly);
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H A D | SetTheory.cpp | 11 // Records from DAG expressions. 195 RecordKeeper &Records = local 207 Record *Rec = Records.getDef(OS.str());
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H A D | CodeGenSchedule.h | 209 RecordKeeper &Records; member in class:llvm::CodeGenSchedModels
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H A D | RegisterInfoEmitter.cpp | 34 RecordKeeper &Records; member in class:__anon10640::RegisterInfoEmitter 36 RegisterInfoEmitter(RecordKeeper &R) : Records(R) {} 1228 Records.getAllDerivedDefinitions("CalleeSavedRegs"); 1254 CodeGenTarget Target(Records);
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H A D | CodeGenRegisters.cpp | 958 CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records) { argument 966 std::vector<Record*> SRIs = Records.getAllDerivedDefinitions("SubRegIndex"); 975 std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register"); 984 Records.getAllDerivedDefinitions("RegisterTuples"); 1022 std::vector<Record*> RCs = Records.getAllDerivedDefinitions("RegisterClass");
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H A D | CodeGenDAGPatterns.cpp | 2005 Records(R), Target(R) { 2007 Intrinsics = LoadIntrinsics(Records, false); 2008 TgtIntrinsics = LoadIntrinsics(Records, true); 2038 Record *N = Records.getDef(Name); 2048 std::vector<Record*> Nodes = Records.getAllDerivedDefinitions("SDNode"); 2063 std::vector<Record*> Xforms = Records.getAllDerivedDefinitions("SDNodeXForm"); 2075 std::vector<Record*> AMs = Records.getAllDerivedDefinitions("ComplexPattern"); 2089 std::vector<Record*> Fragments = Records.getAllDerivedDefinitions("PatFrag"); 2172 DefaultOps = Records.getAllDerivedDefinitions("OperandWithDefaultOps"); 2550 std::vector<Record*> Instrs = Records [all...] |
H A D | CodeGenDAGPatterns.h | 665 RecordKeeper &Records;
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/macosx-10.10.1/llvmCore-3425.0.34/include/llvm/TableGen/ |
H A D | TableGenAction.h | 28 /// Perform the action using Records, and write output to OS. 30 virtual bool operator()(raw_ostream &OS, RecordKeeper &Records) = 0;
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H A D | Record.h | 1 //===- llvm/TableGen/Record.h - Classes for Table Records -------*- C++ -*-===// 1548 MultiClass(const std::string &Name, SMLoc Loc, RecordKeeper &Records) : argument 1549 Rec(Name, Loc, Records) {}
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/macosx-10.10.1/llvmCore-3425.0.34/lib/TableGen/ |
H A D | Main.cpp | 53 RecordKeeper Records; local 73 TGParser Parser(SrcMgr, Records); 107 if (Action(Out.os(), Records))
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H A D | TGParser.h | 70 RecordKeeper &Records; member in class:llvm::TGParser 86 Lex(SrcMgr), CurMultiClass(0), Records(records) {}
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H A D | TGParser.cpp | 360 if (Records.getDef(IterRec->getNameInitAsString())) { 365 Records.addDef(IterRec); 433 Record *Result = Records.getClass(Lex.getCurStrVal()); 792 if (Record *D = Records.getDef(Name)) 1205 Record *Class = Records.getClass(Name); 1224 Records); 1233 Records.addDef(NewRec); 1932 Record *CurRec = new Record(ParseObjectName(CurMultiClass), DefLoc, Records); 1938 if (Records.getDef(CurRec->getNameInitAsString())) { 1943 Records [all...] |