Searched refs:RS1 (Results 1 - 4 of 4) sorted by relevance

/macosx-10.10.1/cxxfilt-11/cxxfilt/include/opcode/
H A Dsparc.h209 #define RS1(x) (((x) & 0x1f) << 14) /* Rs1 field. */ macro
218 #define RS1_G0 RS1 (~0)
/macosx-10.10.1/cxxfilt-11/cxxfilt/opcodes/
H A Dsparc-opc.c683 { "ret", F3(2, 0x38, 1)|RS1(0x1f)|SIMM13(8), F3(~2, ~0x38, ~1)|SIMM13(~8), "", F_UNBR|F_DELAYED, v6 }, /* jmpl %i7+8,%g0 */
684 { "retl", F3(2, 0x38, 1)|RS1(0x0f)|SIMM13(8), F3(~2, ~0x38, ~1)|RS1(~0x0f)|SIMM13(~8), "", F_UNBR|F_DELAYED, v6 }, /* jmpl %o7+8,%g0 */
727 { "membar", F3(2, 0x28, 1)|RS1(0xf), F3(~2, ~0x28, ~1)|RD_G0|RS1(~0xf)|SIMM13(~127), "K", 0, v9 },
728 { "stbar", F3(2, 0x28, 0)|RS1(0xf), F3(~2, ~0x28, ~0)|RD_G0|RS1(~0xf)|SIMM13(~0), "", 0, v8 },
865 { "rd", F3(2, 0x28, 0)|RS1(2), F3(~2, ~0x28, ~0)|RS1(~2)|SIMM13(~0), "E,d", 0, v9 }, /* rd %ccr,r */
866 { "rd", F3(2, 0x28, 0)|RS1(
[all...]
H A Dfr30-opc.c686 { { MNEM, ' ', OP (RS1), ',', OP (RI), 0 } },
698 { { MNEM, ' ', OP (RI), ',', OP (RS1), 0 } },
/macosx-10.10.1/cxxfilt-11/cxxfilt/bfd/
H A Delfxx-sparc.c3412 && (y & RS1(~0)) != RS1(O7)
3440 && (y & (0xffffffff ^ RS1(~0)))
3449 != (INSN_OR | RS1(O7) | RS2(G0)))
3460 reg = (y & RS1(~0)) >> 14;

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