Searched refs:Inst (Results 1 - 25 of 120) sorted by relevance

12345

/macosx-10.10.1/llvmCore-3425.0.34/include/llvm/MC/
H A DMCInstrAnalysis.h31 virtual bool isBranch(const MCInst &Inst) const {
32 return Info->get(Inst.getOpcode()).isBranch();
35 virtual bool isConditionalBranch(const MCInst &Inst) const {
36 return Info->get(Inst.getOpcode()).isConditionalBranch();
39 virtual bool isUnconditionalBranch(const MCInst &Inst) const {
40 return Info->get(Inst.getOpcode()).isUnconditionalBranch();
43 virtual bool isIndirectBranch(const MCInst &Inst) const {
44 return Info->get(Inst.getOpcode()).isIndirectBranch();
47 virtual bool isCall(const MCInst &Inst) const {
48 return Info->get(Inst
[all...]
H A DMCCodeEmitter.h32 /// EncodeInstruction - Encode the given \p Inst to bytes on the output
34 virtual void EncodeInstruction(const MCInst &Inst, raw_ostream &OS,
/macosx-10.10.1/llvmCore-3425.0.34/lib/MC/
H A DMCInstrAnalysis.cpp13 uint64_t MCInstrAnalysis::evaluateBranch(const MCInst &Inst, uint64_t Addr, argument
15 if (Inst.getNumOperands() == 0 ||
16 Info->get(Inst.getOpcode()).OpInfo[0].OperandType != MCOI::OPERAND_PCREL)
19 int64_t Imm = Inst.getOperand(0).getImm();
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/Mips/
H A DMipsDirectObjLower.h23 void LowerLargeShift(MCInst &Inst);
24 void LowerDextDins(MCInst &Inst);
H A DMipsDirectObjLower.cpp23 void Mips::LowerLargeShift(MCInst& Inst) { argument
25 assert(Inst.getNumOperands() == 3 && "Invalid no. of operands for shift!");
26 assert(Inst.getOperand(2).isImm());
30 Shift = Inst.getOperand(2).getImm();
37 (Inst.getOperand(2)).setImm(Shift);
40 switch (Inst.getOpcode()) {
45 Inst.setOpcode(Mips::DSLL32);
48 Inst.setOpcode(Mips::DSRL32);
51 Inst.setOpcode(Mips::DSRA32);
H A DMipsAnalyzeImmediate.h19 struct Inst { struct in class:llvm::MipsAnalyzeImmediate
21 Inst(unsigned Opc, unsigned ImmOpnd);
23 typedef SmallVector<Inst, 7 > InstSeq;
33 void AddInstr(InstSeqLs &SeqLs, const Inst &I);
H A DMipsAnalyzeImmediate.cpp15 MipsAnalyzeImmediate::Inst::Inst(unsigned O, unsigned I) : Opc(O), ImmOpnd(I) {} function in class:MipsAnalyzeImmediate::Inst
18 void MipsAnalyzeImmediate::AddInstr(InstSeqLs &SeqLs, const Inst &I) {
32 AddInstr(SeqLs, Inst(ADDiu, Imm & 0xffffULL));
38 AddInstr(SeqLs, Inst(ORi, Imm & 0xffffULL));
45 AddInstr(SeqLs, Inst(SLL, Shamt));
58 AddInstr(SeqLs, Inst(ADDiu, MaskedImm));
/macosx-10.10.1/llvmCore-3425.0.34/lib/Transforms/Scalar/
H A DEarlyCSE.cpp49 Instruction *Inst; member in struct:__anon10376::SimpleValue
51 SimpleValue(Instruction *I) : Inst(I) {
52 assert((isSentinel() || canHandle(I)) && "Inst can't be handled!");
56 return Inst == DenseMapInfo<Instruction*>::getEmptyKey() ||
57 Inst == DenseMapInfo<Instruction*>::getTombstoneKey();
60 static bool canHandle(Instruction *Inst) { argument
62 if (CallInst *CI = dyn_cast<CallInst>(Inst))
64 return isa<CastInst>(Inst) || isa<BinaryOperator>(Inst) ||
65 isa<GetElementPtrInst>(Inst) || is
92 Instruction *Inst = Val.Inst; local
142 Instruction *Inst; member in struct:__anon10377::CallValue
153 canHandle(Instruction *Inst) argument
184 Instruction *Inst = Val.Inst; local
376 Instruction *Inst = I++; local
481 << *Inst << '\\n'); local
[all...]
H A DSink.cpp58 bool AllUsesDominatedByBlock(Instruction *Inst, BasicBlock *BB) const;
59 bool IsAcceptableTarget(Instruction *Inst, BasicBlock *SuccToSinkTo) const;
74 bool Sinking::AllUsesDominatedByBlock(Instruction *Inst, argument
80 for (Value::use_iterator I = Inst->use_begin(),
81 E = Inst->use_end(); I != E; ++I) {
136 Instruction *Inst = I; // The instruction to sink. local
144 if (isa<DbgInfoIntrinsic>(Inst))
147 if (SinkInstruction(Inst, Stores))
156 static bool isSafeToMove(Instruction *Inst, AliasAnalysis *AA, argument
159 if (Inst
180 IsAcceptableTarget(Instruction *Inst, BasicBlock *SuccToSinkTo) const argument
219 SinkInstruction(Instruction *Inst, SmallPtrSet<Instruction *, 8> &Stores) argument
[all...]
/macosx-10.10.1/llvmCore-3425.0.34/lib/MC/MCDisassembler/
H A DEDOperand.cpp28 Inst(inst),
129 uint8_t operandType = Inst.ThisInstInfo->operandTypes[OpIndex];
142 result = Inst.Inst->getOperand(MCOpIndex).getImm();
146 unsigned reg = Inst.Inst->getOperand(MCOpIndex).getReg();
151 int64_t displacement = Inst.Inst->getOperand(MCOpIndex).getImm();
166 unsigned baseReg = Inst.Inst
[all...]
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/Mips/Disassembler/
H A DMipsDisassembler.cpp101 static DecodeStatus DecodeCPU64RegsRegisterClass(MCInst &Inst,
106 static DecodeStatus DecodeCPURegsRegisterClass(MCInst &Inst,
111 static DecodeStatus DecodeDSPRegsRegisterClass(MCInst &Inst,
116 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
121 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
126 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
131 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
136 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
141 static DecodeStatus DecodeHWRegs64RegisterClass(MCInst &Inst,
146 static DecodeStatus DecodeACRegsRegisterClass(MCInst &Inst,
335 DecodeCPU64RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
348 DecodeCPURegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
359 DecodeDSPRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
366 DecodeFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
378 DecodeFGR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
390 DecodeCCRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
398 DecodeMem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
420 DecodeFMem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
439 DecodeHWRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
450 DecodeCondCode(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
459 DecodeAFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
472 DecodeHWRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
483 DecodeACRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
495 DecodeBranchTarget(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder) argument
505 DecodeBC1(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
515 DecodeJumpTarget(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
526 DecodeSimm16(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
534 DecodeInsSize(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
545 DecodeExtSize(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
[all...]
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp161 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
163 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
166 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
168 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
170 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
172 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
174 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
176 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
178 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst,
182 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigne
913 DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
924 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
936 DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
943 DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
973 DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
990 DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1011 DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1021 DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1029 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1044 DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1064 DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1085 DecodeDPairSpacedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1097 DecodePredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
1111 DecodeCCOutOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
1120 DecodeSOImmOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
1129 DecodeSORegImmOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
1166 DecodeSORegRegOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
1201 DecodeRegListOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
1236 DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
1253 DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
1272 DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
1293 DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1438 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1543 DecodeSORegMemOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
1587 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1778 DecodeRFEInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1807 DecodeMemMultipleWritebackInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1892 DecodeCPSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1932 DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1972 DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1996 DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2022 DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2050 DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
2070 DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
2089 DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
2095 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2122 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2148 DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
2165 DecodeVLDInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2439 DecodeVSTInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2710 DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2757 DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2805 DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2840 DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2895 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2940 DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2959 DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
2965 DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
2971 DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
2977 DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
2983 DecodeTBLInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3019 DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder) argument
3043 DecodeThumbBROperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3051 DecodeT2BROperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3059 DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3067 DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3082 DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3096 DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3106 DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3114 DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3131 DecodeT2LoadShift(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3186 DecodeT2Imm8S4(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3200 DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3215 DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, uint64_t Address, const void *Decoder) argument
3230 DecodeT2Imm8(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3243 DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3274 DecodeT2LdStPre(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3304 DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3319 DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder) argument
3330 DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder) argument
3355 DecodeThumbCPS(MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder) argument
3366 DecodePostIdxReg(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3379 DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3403 DecodeCoprocessor(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3413 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3429 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3471 DecodeT2SOImm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3503 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3511 DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3534 DecodeMemBarrierOption(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3543 DecodeMSRMask(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3550 DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3573 DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3600 DecodeLDRPreImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3625 DecodeLDRPreReg(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3653 DecodeSTRPreImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3678 DecodeSTRPreReg(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3703 DecodeVLD1LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3770 DecodeVST1LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3836 DecodeVLD2LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3903 DecodeVST2LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3967 DecodeVLD3LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4037 DecodeVST3LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4101 DecodeVLD4LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4182 DecodeVST4LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4254 DecodeVMOVSRR(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4280 DecodeVMOVRRS(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4306 DecodeIT(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4328 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4365 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4399 DecodeT2Adr(MCInst &Inst, uint32_t Insn, uint64_t Address, const void *Decoder) argument
4414 DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, uint64_t Address, const void *Decoder) argument
4425 DecodeSwap(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4452 DecodeVCVTD(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4480 DecodeVCVTQ(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4508 DecodeLDR(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
4535 DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
[all...]
/macosx-10.10.1/llvmCore-3425.0.34/tools/llvm-objdump/
H A DMCFunction.cpp55 MCInst Inst; local
56 if (DisAsm->getInstruction(Inst, Size, Region, Index, DebugOut, nulls())){
57 Instructions.push_back(MCDecodedInst(Index, Size, Inst));
58 if (Ana->isBranch(Inst)) {
59 uint64_t targ = Ana->evaluateBranch(Inst, Index, Size);
72 } else if (Ana->isReturn(Inst)) {
76 } else if (Ana->isCall(Inst)) {
77 uint64_t targ = Ana->evaluateBranch(Inst, Index, Size);
116 const MCDecodedInst &Inst = BB.getInsts().back(); local
118 if (Ana->isBranch(Inst
[all...]
H A DMCFunction.h35 MCInst Inst; member in struct:llvm::MCDecodedInst
38 MCDecodedInst(uint64_t Address, uint64_t Size, MCInst Inst) argument
39 : Address(Address), Size(Size), Inst(Inst) {}
61 void addInst(const MCDecodedInst &Inst) { Insts.push_back(Inst); } argument
/macosx-10.10.1/llvmCore-3425.0.34/utils/TableGen/
H A DInstrInfoEmitter.cpp46 void emitRecord(const CodeGenInstruction &Inst, unsigned Num,
54 std::vector<std::string> GetOperandInfo(const CodeGenInstruction &Inst);
71 InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) { argument
74 for (unsigned i = 0, e = Inst.Operands.size(); i != e; ++i) {
83 DagInit *MIOI = Inst.Operands[i].MIOperandInfo;
87 OperandList.push_back(Inst.Operands[i]);
89 for (unsigned j = 0, e = Inst.Operands[i].MINumOperands; j != e; ++j) {
90 OperandList.push_back(Inst.Operands[i]);
120 if (Inst.Operands[i].Rec->isSubClassOf("PredicateOperand"))
125 if (Inst
204 Record *Inst = (*II)->TheDef; local
296 emitRecord(const CodeGenInstruction &Inst, unsigned Num, Record *InstrInfo, std::map<std::vector<Record*>, unsigned> &EmittedLists, const OperandInfoMapTy &OpInfo, raw_ostream &OS) argument
[all...]
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp184 void cvtT2LdrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &);
185 void cvtT2StrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &);
186 void cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst,
188 void cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst,
190 void cvtLdWriteBackRegAddrMode2(MCInst &Inst,
192 void cvtLdWriteBackRegAddrModeImm12(MCInst &Inst,
194 void cvtStWriteBackRegAddrModeImm12(MCInst &Inst,
196 void cvtStWriteBackRegAddrMode2(MCInst &Inst,
198 void cvtStWriteBackRegAddrMode3(MCInst &Inst,
200 void cvtLdExtTWriteBackImm(MCInst &Inst,
1393 addExpr(MCInst &Inst, const MCExpr *Expr) const argument
1403 addCondCodeOperands(MCInst &Inst, unsigned N) const argument
1410 addCoprocNumOperands(MCInst &Inst, unsigned N) const argument
1415 addCoprocRegOperands(MCInst &Inst, unsigned N) const argument
1420 addCoprocOptionOperands(MCInst &Inst, unsigned N) const argument
1425 addITMaskOperands(MCInst &Inst, unsigned N) const argument
1430 addITCondCodeOperands(MCInst &Inst, unsigned N) const argument
1435 addCCOutOperands(MCInst &Inst, unsigned N) const argument
1440 addRegOperands(MCInst &Inst, unsigned N) const argument
1445 addRegShiftedRegOperands(MCInst &Inst, unsigned N) const argument
1455 addRegShiftedImmOperands(MCInst &Inst, unsigned N) const argument
1466 addShifterImmOperands(MCInst &Inst, unsigned N) const argument
1472 addRegListOperands(MCInst &Inst, unsigned N) const argument
1480 addDPRRegListOperands(MCInst &Inst, unsigned N) const argument
1484 addSPRRegListOperands(MCInst &Inst, unsigned N) const argument
1488 addRotImmOperands(MCInst &Inst, unsigned N) const argument
1494 addBitfieldOperands(MCInst &Inst, unsigned N) const argument
1505 addImmOperands(MCInst &Inst, unsigned N) const argument
1510 addFBits16Operands(MCInst &Inst, unsigned N) const argument
1516 addFBits32Operands(MCInst &Inst, unsigned N) const argument
1522 addFPImmOperands(MCInst &Inst, unsigned N) const argument
1529 addImm8s4Operands(MCInst &Inst, unsigned N) const argument
1537 addImm0_1020s4Operands(MCInst &Inst, unsigned N) const argument
1545 addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const argument
1553 addImm0_508s4Operands(MCInst &Inst, unsigned N) const argument
1561 addImm1_16Operands(MCInst &Inst, unsigned N) const argument
1569 addImm1_32Operands(MCInst &Inst, unsigned N) const argument
1577 addImmThumbSROperands(MCInst &Inst, unsigned N) const argument
1586 addPKHASRImmOperands(MCInst &Inst, unsigned N) const argument
1595 addT2SOImmNotOperands(MCInst &Inst, unsigned N) const argument
1603 addT2SOImmNegOperands(MCInst &Inst, unsigned N) const argument
1611 addImm0_4095NegOperands(MCInst &Inst, unsigned N) const argument
1619 addARMSOImmNotOperands(MCInst &Inst, unsigned N) const argument
1627 addARMSOImmNegOperands(MCInst &Inst, unsigned N) const argument
1635 addMemBarrierOptOperands(MCInst &Inst, unsigned N) const argument
1640 addMemNoOffsetOperands(MCInst &Inst, unsigned N) const argument
1645 addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const argument
1653 addAdrLabelOperands(MCInst &Inst, unsigned N) const argument
1669 addAlignedMemoryOperands(MCInst &Inst, unsigned N) const argument
1675 addAddrMode2Operands(MCInst &Inst, unsigned N) const argument
1893 addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const argument
1900 addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const argument
1907 addMemThumbSPIOperands(MCInst &Inst, unsigned N) const argument
1914 addPostIdxImm8Operands(MCInst &Inst, unsigned N) const argument
1925 addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const argument
1937 addPostIdxRegOperands(MCInst &Inst, unsigned N) const argument
1943 addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const argument
1954 addMSRMaskOperands(MCInst &Inst, unsigned N) const argument
1959 addProcIFlagsOperands(MCInst &Inst, unsigned N) const argument
1964 addVecListOperands(MCInst &Inst, unsigned N) const argument
1969 addVecListIndexedOperands(MCInst &Inst, unsigned N) const argument
1975 addVectorIndex8Operands(MCInst &Inst, unsigned N) const argument
1980 addVectorIndex16Operands(MCInst &Inst, unsigned N) const argument
1985 addVectorIndex32Operands(MCInst &Inst, unsigned N) const argument
1990 addNEONi8splatOperands(MCInst &Inst, unsigned N) const argument
1998 addNEONi16splatOperands(MCInst &Inst, unsigned N) const argument
2010 addNEONi32splatOperands(MCInst &Inst, unsigned N) const argument
2024 addNEONi32vmovOperands(MCInst &Inst, unsigned N) const argument
2038 addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const argument
2052 addNEONi64splatOperands(MCInst &Inst, unsigned N) const argument
3882 cvtT2LdrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
3899 cvtT2StrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
3916 cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
3931 cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
3944 cvtLdWriteBackRegAddrMode2(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
3959 cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
3975 cvtStWriteBackRegAddrModeImm12(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
3988 cvtStWriteBackRegAddrMode2(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
4001 cvtStWriteBackRegAddrMode3(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
4014 cvtLdExtTWriteBackImm(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
4032 cvtLdExtTWriteBackReg(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
4050 cvtStExtTWriteBackImm(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
4068 cvtStExtTWriteBackReg(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
4086 cvtLdrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
4103 cvtStrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
4120 cvtLdWriteBackRegAddrMode3(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
4133 cvtThumbMultiply(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
4150 cvtVLDwbFixed(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
4163 cvtVLDwbRegister(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
4178 cvtVSTwbFixed(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
4191 cvtVSTwbRegister(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
5197 checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg, unsigned HiReg, bool &containsReg) argument
5213 listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) argument
5234 validateInstruction(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
5669 processInstruction(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
7435 checkTargetMatchPredicate(MCInst &Inst) argument
7483 MCInst Inst; local
[all...]
/macosx-10.10.1/llvmCore-3425.0.34/lib/Analysis/
H A DPHITransAddr.cpp25 static bool CanPHITrans(Instruction *Inst) { argument
26 if (isa<PHINode>(Inst) ||
27 isa<GetElementPtrInst>(Inst))
30 if (isa<CastInst>(Inst) &&
31 isSafeToSpeculativelyExecute(Inst))
34 if (Inst->getOpcode() == Instruction::Add &&
35 isa<ConstantInt>(Inst->getOperand(1)))
118 Instruction *Inst = dyn_cast<Instruction>(Addr); local
119 return Inst == 0 || CanPHITrans(Inst);
149 Instruction *Inst = dyn_cast<Instruction>(V); local
[all...]
H A DMemDepPrinter.cpp102 Instruction *Inst = &*I; local
104 if (!Inst->mayReadFromMemory() && !Inst->mayWriteToMemory())
107 MemDepResult Res = MDA.getDependency(Inst);
109 Deps[Inst].insert(std::make_pair(getInstTypePair(Res),
111 } else if (CallSite CS = cast<Value>(Inst)) {
115 DepSet &InstDeps = Deps[Inst];
123 if (LoadInst *LI = dyn_cast<LoadInst>(Inst)) {
126 Deps[Inst].insert(std::make_pair(getInstTypePair(0, Unknown),
132 } else if (StoreInst *SI = dyn_cast<StoreInst>(Inst)) {
162 const Instruction *Inst = &*I; local
[all...]
H A DMemoryDependenceAnalysis.cpp100 /// 'Inst's set in ReverseMap. If the set becomes empty, remove Inst's entry.
104 Instruction *Inst, KeyTy Val) {
106 InstIt = ReverseMap.find(Inst);
119 AliasAnalysis::ModRefResult GetLocation(const Instruction *Inst, argument
122 if (const LoadInst *LI = dyn_cast<LoadInst>(Inst)) {
134 if (const StoreInst *SI = dyn_cast<StoreInst>(Inst)) {
146 if (const VAArgInst *V = dyn_cast<VAArgInst>(Inst)) {
151 if (const CallInst *CI = isFreeCall(Inst, AA->getTargetLibraryInfo())) {
157 if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(Inst))
102 RemoveFromReverseMap(DenseMap<Instruction*, SmallPtrSet<KeyTy, 4> > &ReverseMap, Instruction *Inst, KeyTy Val) argument
[all...]
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/MBlaze/MCTargetDesc/
H A DMBlazeAsmBackend.cpp53 bool mayNeedRelaxation(const MCInst &Inst) const;
60 void relaxInstruction(const MCInst &Inst, MCInst &Res) const;
78 bool MBlazeAsmBackend::mayNeedRelaxation(const MCInst &Inst) const {
79 if (getRelaxedOpcode(Inst.getOpcode()) == Inst.getOpcode())
83 for (unsigned i = 0; i < Inst.getNumOperands(); ++i)
84 hasExprOrImm |= Inst.getOperand(i).isExpr();
101 void MBlazeAsmBackend::relaxInstruction(const MCInst &Inst, MCInst &Res) const { argument
102 Res = Inst;
103 Res.setOpcode(getRelaxedOpcode(Inst
[all...]
/macosx-10.10.1/llvmCore-3425.0.34/lib/Transforms/Instrumentation/
H A DBoundsChecking.cpp60 Instruction *Inst; member in struct:__anon10359::BoundsChecking
83 Function *Fn = Inst->getParent()->getParent();
92 TrapCall->setDebugLoc(Inst->getDebugLoc());
113 Instruction *Inst = Builder->GetInsertPoint(); local
114 BasicBlock *OldBB = Inst->getParent();
115 BasicBlock *Cont = OldBB->splitBasicBlock(Inst);
146 IntegerType *IntTy = TD->getIntPtrType(Inst->getContext());
193 Inst = *i;
195 Builder->SetInsertPoint(Inst);
196 if (LoadInst *LI = dyn_cast<LoadInst>(Inst)) {
[all...]
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp71 bool processInstruction(MCInst &Inst,
395 void addExpr(MCInst &Inst, const MCExpr *Expr) const { argument
398 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
400 Inst.addOperand(MCOperand::CreateExpr(Expr));
403 void addRegOperands(MCInst &Inst, unsigned N) const { argument
405 Inst.addOperand(MCOperand::CreateReg(getReg()));
408 void addImmOperands(MCInst &Inst, unsigned N) const { argument
410 addExpr(Inst, getImm());
413 void addMem8Operands(MCInst &Inst, unsigned N) const { argument
414 addMemOperands(Inst,
416 addMem16Operands(MCInst &Inst, unsigned N) const argument
419 addMem32Operands(MCInst &Inst, unsigned N) const argument
422 addMem64Operands(MCInst &Inst, unsigned N) const argument
425 addMem80Operands(MCInst &Inst, unsigned N) const argument
428 addMem128Operands(MCInst &Inst, unsigned N) const argument
431 addMem256Operands(MCInst &Inst, unsigned N) const argument
434 addMemVX32Operands(MCInst &Inst, unsigned N) const argument
437 addMemVY32Operands(MCInst &Inst, unsigned N) const argument
440 addMemVX64Operands(MCInst &Inst, unsigned N) const argument
443 addMemVY64Operands(MCInst &Inst, unsigned N) const argument
447 addMemOperands(MCInst &Inst, unsigned N) const argument
456 addAbsMemOperands(MCInst &Inst, unsigned N) const argument
1513 processInstruction(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Ops) argument
1769 MCInst Inst; local
1792 MCInst Inst; local
[all...]
/macosx-10.10.1/llvmCore-3425.0.34/lib/Transforms/Utils/
H A DLCSSA.cpp75 bool ProcessInstruction(Instruction *Inst,
178 bool LCSSA::ProcessInstruction(Instruction *Inst, argument
182 BasicBlock *InstBB = Inst->getParent();
184 for (Value::use_iterator UI = Inst->use_begin(), E = Inst->use_end();
204 BasicBlock *DomBB = Inst->getParent();
205 if (InvokeInst *Inv = dyn_cast<InvokeInst>(Inst))
213 SSAUpdate.Initialize(Inst->getType(), Inst->getName());
225 PHINode *PN = PHINode::Create(Inst
[all...]
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/ARM/MCTargetDesc/
H A DARMMCTargetDesc.cpp209 virtual bool isUnconditionalBranch(const MCInst &Inst) const {
211 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
213 return MCInstrAnalysis::isUnconditionalBranch(Inst);
216 virtual bool isConditionalBranch(const MCInst &Inst) const {
218 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
220 return MCInstrAnalysis::isConditionalBranch(Inst);
223 uint64_t evaluateBranch(const MCInst &Inst, uint64_t Addr, argument
226 if (Info->get(Inst
[all...]
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/MBlaze/AsmParser/
H A DMBlazeAsmParser.cpp176 void addExpr(MCInst &Inst, const MCExpr *Expr) const { argument
179 Inst.addOperand(MCOperand::CreateImm(0));
181 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
183 Inst.addOperand(MCOperand::CreateExpr(Expr));
186 void addRegOperands(MCInst &Inst, unsigned N) const { argument
188 Inst.addOperand(MCOperand::CreateReg(getReg()));
191 void addImmOperands(MCInst &Inst, unsigned N) const { argument
193 addExpr(Inst, getImm());
196 void addFslOperands(MCInst &Inst, unsigned N) const { argument
198 addExpr(Inst, getFslIm
201 addMemOperands(MCInst &Inst, unsigned N) const argument
321 MCInst Inst; local
[all...]

Completed in 374 milliseconds

12345