Lines Matching refs:Inst
46 void emitRecord(const CodeGenInstruction &Inst, unsigned Num,
54 std::vector<std::string> GetOperandInfo(const CodeGenInstruction &Inst);
71 InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
74 for (unsigned i = 0, e = Inst.Operands.size(); i != e; ++i) {
83 DagInit *MIOI = Inst.Operands[i].MIOperandInfo;
87 OperandList.push_back(Inst.Operands[i]);
89 for (unsigned j = 0, e = Inst.Operands[i].MINumOperands; j != e; ++j) {
90 OperandList.push_back(Inst.Operands[i]);
120 if (Inst.Operands[i].Rec->isSubClassOf("PredicateOperand"))
125 if (Inst.Operands[i].Rec->isSubClassOf("OptionalDefOperand"))
130 assert(!Inst.Operands[i].OperandType.empty() && "Invalid operand type.");
131 Res += Inst.Operands[i].OperandType;
137 Inst.Operands[i].Constraints[j];
204 Record *Inst = (*II)->TheDef;
205 std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses");
210 std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs");
296 void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
302 if (!Inst.Operands.size() == 0)
304 MinOperands = Inst.Operands.back().MIOperandNo +
305 Inst.Operands.back().MINumOperands;
309 << Inst.Operands.NumDefs << ",\t"
310 << SchedModels.getSchedClassIdx(Inst) << ",\t"
311 << Inst.TheDef->getValueAsInt("Size") << ",\t0";
314 if (Inst.isPseudo) OS << "|(1<<MCID::Pseudo)";
315 if (Inst.isReturn) OS << "|(1<<MCID::Return)";
316 if (Inst.isBranch) OS << "|(1<<MCID::Branch)";
317 if (Inst.isIndirectBranch) OS << "|(1<<MCID::IndirectBranch)";
318 if (Inst.isCompare) OS << "|(1<<MCID::Compare)";
319 if (Inst.isMoveImm) OS << "|(1<<MCID::MoveImm)";
320 if (Inst.isBitcast) OS << "|(1<<MCID::Bitcast)";
321 if (Inst.isSelect) OS << "|(1<<MCID::Select)";
322 if (Inst.isBarrier) OS << "|(1<<MCID::Barrier)";
323 if (Inst.hasDelaySlot) OS << "|(1<<MCID::DelaySlot)";
324 if (Inst.isCall) OS << "|(1<<MCID::Call)";
325 if (Inst.canFoldAsLoad) OS << "|(1<<MCID::FoldableAsLoad)";
326 if (Inst.mayLoad) OS << "|(1<<MCID::MayLoad)";
327 if (Inst.mayStore) OS << "|(1<<MCID::MayStore)";
328 if (Inst.isPredicable) OS << "|(1<<MCID::Predicable)";
329 if (Inst.isConvertibleToThreeAddress) OS << "|(1<<MCID::ConvertibleTo3Addr)";
330 if (Inst.isCommutable) OS << "|(1<<MCID::Commutable)";
331 if (Inst.isTerminator) OS << "|(1<<MCID::Terminator)";
332 if (Inst.isReMaterializable) OS << "|(1<<MCID::Rematerializable)";
333 if (Inst.isNotDuplicable) OS << "|(1<<MCID::NotDuplicable)";
334 if (Inst.Operands.hasOptionalDef) OS << "|(1<<MCID::HasOptionalDef)";
335 if (Inst.usesCustomInserter) OS << "|(1<<MCID::UsesCustomInserter)";
336 if (Inst.hasPostISelHook) OS << "|(1<<MCID::HasPostISelHook)";
337 if (Inst.Operands.isVariadic)OS << "|(1<<MCID::Variadic)";
338 if (Inst.hasSideEffects) OS << "|(1<<MCID::UnmodeledSideEffects)";
339 if (Inst.isAsCheapAsAMove) OS << "|(1<<MCID::CheapAsAMove)";
340 if (Inst.hasExtraSrcRegAllocReq) OS << "|(1<<MCID::ExtraSrcRegAllocReq)";
341 if (Inst.hasExtraDefRegAllocReq) OS << "|(1<<MCID::ExtraDefRegAllocReq)";
344 BitsInit *TSF = Inst.TheDef->getValueAsBitsInit("TSFlags");
351 throw "Invalid TSFlags bit in " + Inst.TheDef->getName();
358 std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses");
364 std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
371 std::vector<std::string> OperandInfo = GetOperandInfo(Inst);
377 OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";