Searched refs:BuildMI (Results 1 - 25 of 94) sorted by relevance

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/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/NVPTX/
H A DNVPTXFrameLowering.cpp45 MachineInstr *MI = BuildMI(MBB, MBBI, dl,
48 BuildMI(MBB, MI, dl,
52 MachineInstr *MI = BuildMI(MBB, MBBI, dl,
55 BuildMI(MBB, MI, dl,
63 BuildMI(MBB, MBBI, dl,
67 BuildMI(MBB, MBBI, dl,
H A DNVPTXInstrInfo.cpp42 BuildMI(MBB, I, DL, get(NVPTX::IMOV32rr), DestReg)
46 BuildMI(MBB, I, DL, get(NVPTX::IMOV8rr), DestReg)
50 BuildMI(MBB, I, DL, get(NVPTX::IMOV1rr), DestReg)
54 BuildMI(MBB, I, DL, get(NVPTX::FMOV32rr), DestReg)
58 BuildMI(MBB, I, DL, get(NVPTX::IMOV16rr), DestReg)
62 BuildMI(MBB, I, DL, get(NVPTX::IMOV64rr), DestReg)
66 BuildMI(MBB, I, DL, get(NVPTX::FMOV64rr), DestReg)
70 BuildMI(MBB, I, DL, get(NVPTX::V4f32Mov), DestReg)
74 BuildMI(MBB, I, DL, get(NVPTX::V4i32Mov), DestReg)
78 BuildMI(MB
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/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/Hexagon/
H A DHexagonExpandPredSpillCode.cpp89 BuildMI(*MBB, MII, MI->getDebugLoc(),
92 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::ADD_rr),
95 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_RsPd),
97 BuildMI(*MBB, MII, MI->getDebugLoc(),
102 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::ADD_ri),
104 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_RsPd),
106 BuildMI(*MBB, MII, MI->getDebugLoc(),
113 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_RsPd),
115 BuildMI(*MBB, MII, MI->getDebugLoc(),
133 BuildMI(*MB
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H A DHexagonSplitTFRCondSets.cpp106 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Opc1),
110 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Opc2),
125 BuildMI(*MBB, MII, MI->getDebugLoc(),
130 BuildMI(*MBB, MII, MI->getDebugLoc(),
135 BuildMI(*MBB, MII, MI->getDebugLoc(),
151 BuildMI(*MBB, MII, MI->getDebugLoc(),
156 BuildMI(*MBB, MII, MI->getDebugLoc(),
165 BuildMI(*MBB, MII, MI->getDebugLoc(),
181 BuildMI(*MBB, MII, MI->getDebugLoc(),
184 BuildMI(*MB
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H A DHexagonRegisterInfo.cpp197 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
199 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
203 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
226 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
228 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
232 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
246 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
248 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
254 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
262 BuildMI(*M
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/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/Sparc/
H A DSparcFrameLowering.cpp55 BuildMI(MBB, MBBI, dl, TII.get(SP::SAVEri), SP::O6)
61 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
63 BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1)
65 BuildMI(MBB, MBBI, dl, TII.get(SP::SAVErr), SP::O6)
78 BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
H A DSparcInstrInfo.cpp121 MachineInstrBuilder MIB = BuildMI(MF, dl, get(SP::DBG_VALUE))
205 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(Opcode))
207 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(SP::BA))
240 BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB);
248 BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC);
250 BuildMI(&MBB, DL, get(SP::FBCOND)).addMBB(TBB).addImm(CC);
254 BuildMI(&MBB, DL, get(SP::BA)).addMBB(FBB);
285 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0)
288 BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg)
291 BuildMI(MB
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/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/CellSPU/
H A DSPUFrameLowering.cpp120 BuildMI(MBB, MBBI, dl, TII.get(SPU::PROLOG_LABEL)).addSym(FrameLabel);
125 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R0).addImm(16)
129 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R1).addImm(FrameSize)
132 BuildMI(MBB, MBBI, dl, TII.get(SPU::AIr32), SPU::R1).addReg(SPU::R1)
137 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr128), SPU::R2)
140 BuildMI(MBB, MBBI, dl, TII.get(SPU::ILr32), SPU::R2)
142 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQXr32), SPU::R1)
145 BuildMI(MBB, MBBI, dl, TII.get(SPU::Ar32), SPU::R1)
148 BuildMI(MBB, MBBI, dl, TII.get(SPU::SFIr32), SPU::R2)
151 BuildMI(MB
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H A DSPUNopFiller.cpp96 BuildMI(MBB, I, I->getDebugLoc(), TII->get(SPU::ENOP));
105 BuildMI(MBB, I, I->getDebugLoc(), TII->get(SPU::LNOP));
121 BuildMI(MBB, J, J->getDebugLoc(), TII->get(SPU::ENOP));
126 BuildMI(MBB, J, DebugLoc(), TII->get(SPU::LNOP));
H A DSPUInstrInfo.cpp134 BuildMI(MBB, I, DL, get(SPU::LRr128), DestReg)
167 addFrameReference(BuildMI(MBB, MI, DL, get(opc))
200 addFrameReference(BuildMI(MBB, MI, DL, get(opc), DestReg), FrameIdx);
364 MIB = BuildMI(&MBB, DL, get(SPU::HBR_LABEL)).addSym(branchLabel);
370 MIB = BuildMI(&MBB, DL, get(SPU::BR));
378 MIB = BuildMI( MBB, findHBRPosition(MBB), DL, get(SPU::HBRA));
384 MIB = BuildMI(&MBB, DL, get(Cond[0].getImm()));
388 MIB = BuildMI(MBB, findHBRPosition(MBB), DL, get(SPU::HBRA));
398 MIB = BuildMI(&MBB, DL, get(Cond[0].getImm()));
399 MachineInstrBuilder MIB2 = BuildMI(
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/macosx-10.10.1/llvmCore-3425.0.34/include/llvm/CodeGen/
H A DMachineInstrBuilder.h10 // This file exposes a function named BuildMI, which is useful for dramatically
13 // M = BuildMI(X86::ADDrr8, 2).addReg(argVal1).addReg(argVal2);
201 /// BuildMI - Builder interface. Specify how to create the initial instruction
204 inline MachineInstrBuilder BuildMI(MachineFunction &MF, function in namespace:llvm
210 /// BuildMI - This version of the builder sets up the first operand as a
213 inline MachineInstrBuilder BuildMI(MachineFunction &MF, function in namespace:llvm
221 /// BuildMI - This version of the builder inserts the newly-built
225 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, function in namespace:llvm
235 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, function in namespace:llvm
245 inline MachineInstrBuilder BuildMI(MachineBasicBloc function in namespace:llvm
263 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, function in namespace:llvm
272 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, function in namespace:llvm
281 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, function in namespace:llvm
298 inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, function in namespace:llvm
308 inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, function in namespace:llvm
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/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/Mips/
H A DMipsLongBranch.cpp223 MachineInstrBuilder MIB = BuildMI(MBB, Br, DL, NewDesc);
282 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
284 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)).addReg(Mips::RA)
286 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::BAL_BR)).addMBB(BalTgtMBB);
287 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LUi), Mips::AT).addImm(Hi)
292 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::AT)
294 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDu), Mips::AT)
296 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LW), Mips::RA)
298 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::JR)).addReg(Mips::AT);
299 BuildMI(*BalTgtMB
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H A DMips16InstrInfo.cpp70 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
94 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
111 BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(0)
144 BuildMI(MBB, I, I->getDebugLoc(), get(Opc));
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp182 return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
206 BuildMI(MBB, MI, DL, get(PPC::NOP));
390 BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
392 BuildMI(&MBB, DL, get(Cond[0].getImm() ?
396 BuildMI(&MBB, DL, get(PPC::BCC))
403 BuildMI(&MBB, DL, get(Cond[0].getImm() ?
407 BuildMI(&MBB, DL, get(PPC::BCC))
409 BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
435 BuildMI(MBB, I, DL, MCID, DestReg)
438 BuildMI(MB
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H A DPPCFrameLowering.cpp137 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
141 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
146 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
150 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
155 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
159 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
163 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
329 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR8), PPC::X0);
332 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD))
338 BuildMI(MB
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H A DPPCBranchSelector.cpp152 BuildMI(MBB, I, dl, TII->get(PPC::BCC))
155 BuildMI(MBB, I, dl, TII->get(PPC::BDZ)).addImm(2);
157 BuildMI(MBB, I, dl, TII->get(PPC::BDZ8)).addImm(2);
159 BuildMI(MBB, I, dl, TII->get(PPC::BDNZ)).addImm(2);
161 BuildMI(MBB, I, dl, TII->get(PPC::BDNZ8)).addImm(2);
167 I = BuildMI(MBB, I, dl, TII->get(PPC::B)).addMBB(Dest);
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/XCore/
H A DXCoreRegisterInfo.cpp139 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode))
144 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode), XCore::SP)
229 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
234 BuildMI(MBB, II, dl, TII.get(XCore::STW_3r))
240 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
250 BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg)
255 BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus))
261 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg)
279 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
284 BuildMI(MB
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H A DXCoreInstrInfo.cpp287 BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(TBB);
291 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
300 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
302 BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(FBB);
342 BuildMI(MBB, I, DL, get(XCore::ADD_2rus), DestReg)
349 BuildMI(MBB, I, DL, get(XCore::LDAWSP_ru6), DestReg).addImm(0);
354 BuildMI(MBB, I, DL, get(XCore::SETSP_1r))
370 BuildMI(MBB, I, DL, get(XCore::STWFI))
384 BuildMI(MBB, I, DL, get(XCore::LDWFI), DestReg)
393 MachineInstrBuilder MIB = BuildMI(M
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H A DXCoreFrameLowering.cpp55 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg)
70 BuildMI(MBB, I, dl, TII.get(Opcode))
134 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize);
141 BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(FrameLabel);
160 BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(SaveLRLabel);
176 BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(SaveR10Label);
183 BuildMI(MBB, MBBI, dl, TII.get(XCore::LDAWSP_ru6), FramePtr)
188 BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(FrameLabel);
224 BuildMI(MBB, MBBI, dl, TII.get(XCore::SETSP_1r))
263 BuildMI(MB
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/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/MSP430/
H A DMSP430FrameLowering.cpp66 BuildMI(MBB, MBBI, DL, TII.get(MSP430::PUSH16r))
70 BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::FPW)
98 BuildMI(MBB, MBBI, DL, TII.get(MSP430::SUB16ri), MSP430::SPW)
135 BuildMI(MBB, MBBI, DL, TII.get(MSP430::POP16r), MSP430::FPW);
156 BuildMI(MBB, MBBI, DL,
160 BuildMI(MBB, MBBI, DL,
170 BuildMI(MBB, MBBI, DL, TII.get(MSP430::ADD16ri), MSP430::SPW)
199 BuildMI(MBB, MI, DL, TII.get(MSP430::PUSH16r))
220 BuildMI(MBB, MI, DL, TII.get(MSP430::POP16r), CSI[i].getReg());
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/MBlaze/
H A DMBlazeFrameLowering.cpp255 BuildMI(MENT, MENTI, ENTDL, TII.get(MBlaze::SWI), r)
263 BuildMI(MENT, MENTI, ENTDL, TII.get(MBlaze::SWI), MBlaze::R17)
266 BuildMI(MENT, MENTI, ENTDL, TII.get(MBlaze::SWI), MBlaze::R18)
272 BuildMI(MENT, MENTI, ENTDL, TII.get(MBlaze::MFS), MBlaze::R11)
274 BuildMI(MENT, MENTI, ENTDL, TII.get(MBlaze::SWI), MBlaze::R11)
277 BuildMI(MEXT, MEXTI, EXTDL, TII.get(MBlaze::LWI), MBlaze::R11)
279 BuildMI(MEXT, MEXTI, EXTDL, TII.get(MBlaze::MTS), MBlaze::RMSR)
284 BuildMI(MEXT, MEXTI, EXTDL, TII.get(MBlaze::LWI), MBlaze::R18)
287 BuildMI(MEXT, MEXTI, EXTDL, TII.get(MBlaze::LWI), MBlaze::R17)
293 BuildMI(MEX
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H A DMBlazeInstrInfo.cpp80 BuildMI(MBB, MI, DL, get(MBlaze::NOP));
88 llvm::BuildMI(MBB, I, DL, get(MBlaze::ADDK), DestReg)
98 BuildMI(MBB, I, DL, get(MBlaze::SWI)).addReg(SrcReg,getKillRegState(isKill))
108 BuildMI(MBB, I, DL, get(MBlaze::LWI), DestReg)
202 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
204 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()).addMBB(TBB);
208 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()).addMBB(TBB);
209 BuildMI(&MBB, DL, get(MBlaze::BRID)).addMBB(FBB);
291 BuildMI(FirstMBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY),
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/ARM/
H A DThumb1InstrInfo.cpp45 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
73 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSTRspi))
101 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tLDRspi), DestReg)
H A DThumb2RegisterInfo.cpp48 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2LDRpci))
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/X86/
H A DX86FrameLowering.cpp174 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc))
186 MI = addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
189 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
694 BuildMI(MBB, MBBI, DL,
740 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
747 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL))
768 BuildMI(MBB, MBBI, DL,
776 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL))
807 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)).addSym(Label);
829 BuildMI(MB
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