Searched refs:BaseOffs (Results 1 - 15 of 15) sorted by relevance

/macosx-10.10.1/llvmCore-3425.0.34/include/llvm/Transforms/Utils/
H A DAddrModeMatcher.h45 (BaseGV == O.BaseGV) && (BaseOffs == O.BaseOffs) &&
/macosx-10.10.1/llvmCore-3425.0.34/lib/Transforms/Utils/
H A DAddrModeMatcher.cpp39 if (BaseOffs)
40 OS << (NeedPlus ? " + " : "") << BaseOffs, NeedPlus = true;
106 TestAddrMode.BaseOffs += CI->getSExtValue()*TestAddrMode.Scale;
251 AddrMode.BaseOffs += ConstantOffset;
257 AddrMode.BaseOffs -= ConstantOffset;
266 AddrMode.BaseOffs += ConstantOffset;
291 AddrMode.BaseOffs += ConstantOffset;
315 AddrMode.BaseOffs += CI->getSExtValue();
318 AddrMode.BaseOffs -= CI->getSExtValue();
/macosx-10.10.1/llvmCore-3425.0.34/lib/Transforms/Scalar/
H A DLoopStrengthReduce.cpp388 if (AM.BaseOffs != 0) {
390 OS << AM.BaseOffs;
929 int64_t Offset = (uint64_t)*I + F.AM.BaseOffs;
1282 return !AM.BaseGV && AM.BaseOffs == 0 && AM.Scale <= 1;
1291 if (AM.Scale != 0 && AM.HasBaseReg && AM.BaseOffs != 0)
1301 if (AM.BaseOffs != 0) {
1308 int64_t Offs = AM.BaseOffs;
1319 return !AM.BaseGV && AM.Scale == 0 && AM.BaseOffs == 0;
1323 return !AM.BaseGV && (AM.Scale == 0 || AM.Scale == -1) && AM.BaseOffs == 0;
1334 if (((int64_t)((uint64_t)AM.BaseOffs
1350 isAlwaysFoldable(int64_t BaseOffs, GlobalValue *BaseGV, bool HasBaseReg, LSRUse::KindType Kind, Type *AccessTy, const TargetLowering *TLI) argument
[all...]
H A DCodeGenPrepare.cpp1068 if (AddrMode.BaseOffs) {
1069 Value *V = ConstantInt::get(IntPtrTy, AddrMode.BaseOffs);
/macosx-10.10.1/llvmCore-3425.0.34/lib/Analysis/
H A DBasicAliasAnalysis.cpp234 DecomposeGEPExpression(const Value *V, int64_t &BaseOffs, argument
240 BaseOffs = 0;
301 BaseOffs += TD->getStructLayout(STy)->getElementOffset(FieldNo);
308 BaseOffs += TD->getTypeAllocSize(*GTI)*CIdx->getSExtValue();
328 BaseOffs += IndexOffset.getSExtValue()*Scale;
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/XCore/
H A DXCoreISelLowering.cpp1571 return AM.Scale == 0 && isImmUs(AM.BaseOffs) && isImmUs4(AM.BaseOffs);
1577 AM.BaseOffs%4 == 0;
1584 return isImmUs(AM.BaseOffs);
1587 return AM.Scale == 1 && AM.BaseOffs == 0;
1592 return isImmUs2(AM.BaseOffs);
1595 return AM.Scale == 2 && AM.BaseOffs == 0;
1599 return isImmUs4(AM.BaseOffs);
1602 return AM.Scale == 4 && AM.BaseOffs == 0;
/macosx-10.10.1/llvmCore-3425.0.34/include/llvm/Target/
H A DTargetLowering.h1636 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1638 /// If BaseOffs is zero, there is no base offset.
1645 int64_t BaseOffs;
1648 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {}
/macosx-10.10.1/llvmCore-3425.0.34/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp3269 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
3281 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
3286 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
H A DDAGCombiner.cpp6722 AM.BaseOffs = Offset->getSExtValue();
6730 AM.BaseOffs = -Offset->getSExtValue();
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1558 if (AM.BaseOffs <= -(1LL << 13) || AM.BaseOffs >= (1LL << 13)-1) {
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/CellSPU/
H A DSPUISelLowering.cpp3254 if (AM.BaseGV && !AM.HasBaseReg && AM.Scale == 0 && AM.BaseOffs == 0)
3258 if (AM.BaseGV ==0 && AM.HasBaseReg && AM.Scale == 0 && isInt<14>(AM.BaseOffs))
3262 if (AM.BaseGV == 0 && AM.HasBaseReg && AM.Scale == 1 && AM.BaseOffs ==0)
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp1207 // BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1216 if (AM.BaseOffs || AM.HasBaseReg || AM.Scale)
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/PowerPC/
H A DPPCISelLowering.cpp5916 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
5928 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
5933 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/ARM/
H A DARMISelLowering.cpp9253 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
9269 if (AM.BaseOffs)
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/X86/
H A DX86ISelLowering.cpp11806 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
11824 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))

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