Searched refs:getInstr (Results 1 - 13 of 13) sorted by relevance

/macosx-10.10/llvmCore-3425.0.34/lib/Target/ARM/
H A DARMHazardRecognizer.cpp38 MachineInstr *MI = SU->getInstr();
80 MachineInstr *MI = SU->getInstr();
/macosx-10.10/llvmCore-3425.0.34/lib/CodeGen/
H A DScheduleDAGInstrs.cpp232 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx);
253 MachineInstr *RegUse = UseOp < 0 ? 0 : UseSU->getInstr();
255 SchedModel.computeOperandLatency(SU->getInstr(), OperIdx,
258 SchedModel.computeOperandLatency(SU->getInstr(), OperIdx,
271 const MachineInstr *MI = SU->getInstr();
292 !DefSU->getInstr()->registerDefIsDead(*Alias))) {
297 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr());
345 const MachineInstr *MI = SU->getInstr();
368 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr());
382 MachineInstr *MI = SU->getInstr();
[all...]
H A DSlotIndexes.cpp152 if (itr->getInstr() != 0) {
153 dbgs() << *itr->getInstr();
H A DDFAPacketizer.cpp170 MIToSUnit[SU->getInstr()] = SU;
H A DCriticalAntiDepBreaker.cpp431 MISUnitMap[SU->getInstr()] = SU;
452 MachineInstr *CriticalPathMI = CriticalPathSU->getInstr();
557 CriticalPathMI = CriticalPathSU->getInstr();
H A DMachineScheduler.cpp558 MachineInstr *MI = SU->getInstr();
791 assert(SU->getInstr() && "Scheduled SUnit must have instr");
823 unsigned uops = SchedModel->getNumMicroOps(SU->getInstr());
883 IssueCount += SchedModel->getNumMicroOps(SU->getInstr());
1000 TempTracker.getMaxPressureDelta((*I)->getInstr(), RPDelta,
1257 DEBUG(dbgs() << "*** Scheduling " << *SU->getInstr()
H A DAggressiveAntiDepBreaker.cpp737 MISUnitMap.insert(std::pair<MachineInstr *, const SUnit *>(SU->getInstr(),
756 CriticalPathMI = CriticalPathSU->getInstr();
801 CriticalPathMI = (CriticalPathSU) ? CriticalPathSU->getInstr() : 0;
H A DPostRASchedulerList.cpp771 BB->splice(RegionEnd, BB, SU->getInstr());
/macosx-10.10/llvmCore-3425.0.34/lib/Target/Hexagon/
H A DHexagonMachineScheduler.cpp30 if (SUnits[su].getInstr()->isCall())
33 else if (SUnits[su].getInstr()->isCompare() && LastSequentialCall)
45 if (!SU || !SU->getInstr())
50 switch (SU->getInstr()->getOpcode()) {
52 if (!ResourcesModel->canReserveResources(SU->getInstr()))
102 switch (SU->getInstr()->getOpcode()) {
104 ResourcesModel->reserveResources(SU->getInstr());
125 DEBUG(Packet[i]->getInstr()->dump());
229 assert(SU->getInstr() && "Scheduled SUnit must have instr");
261 unsigned uops = SchedModel->getNumMicroOps(SU->getInstr());
[all...]
H A DHexagonVLIWPacketizer.cpp2807 if (PacketSU->getInstr()->getDesc().mayStore() ||
2810 PacketSU->getInstr()->getOpcode() == Hexagon::ALLOCFRAME ||
2811 PacketSU->getInstr()->getOpcode() == Hexagon::DEALLOCFRAME)
2907 MachineInstr* TempMI = TempSU->getInstr();
2921 TempSU->getInstr()->modifiesRegister(MI->getOperand(opNum).getReg(),
2974 MachineInstr *PacketMI = PacketSU->getInstr();
3214 MachineInstr *I = SUI->getInstr();
3215 MachineInstr *J = SUJ->getInstr();
3327 if (PacketSU->getInstr()->getDesc().isCall()) {
3339 if (PacketSU->getInstr()
[all...]
/macosx-10.10/llvmCore-3425.0.34/lib/Target/PowerPC/
H A DPPCHazardRecognizers.cpp140 MachineInstr *MI = SU->getInstr();
198 MachineInstr *MI = SU->getInstr();
/macosx-10.10/llvmCore-3425.0.34/include/llvm/CodeGen/
H A DSlotIndexes.h45 MachineInstr* getInstr() const { return mi; } function in class:llvm::IndexListEntry
390 return index.isValid() ? index.listEntry()->getInstr() : 0;
397 while (itr != indexList.end() && itr->getInstr() == 0) { ++itr; }
578 assert(miEntry->getInstr() == mi && "Instruction indexes broken.");
593 assert(miEntry->getInstr() == mi &&
H A DScheduleDAG.h367 /// getInstr - Return the representative MachineInstr for this SUnit.
369 MachineInstr *getInstr() const { function in class:llvm::SUnit
544 if (SU->isInstr()) return &SU->getInstr()->getDesc();

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