Searched refs:XOR (Results 1 - 25 of 178) sorted by relevance

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/macosx-10.10/swig-12/Source/CParse/
H A Dparser.h153 XOR = 369, enumerator in enum:yytokentype
280 #define XOR 369 macro
H A Dcscanner.c318 return XOR;
/macosx-10.10/llvmCore-3425.0.34/include/llvm/CodeGen/
H A DISDOpcodes.h307 AND, OR, XOR, enumerator in enum:llvm::ISD::NodeType
/macosx-10.10/llvmCore-3425.0.34/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp64 // Implement vselect in terms of XOR, AND, OR when blend is not supported
186 case ISD::XOR:
445 // using XOR AND OR. The selector bit is broadcasted.
459 // AND,OR,XOR, we will have to scalarize the op.
464 TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand ||
494 SDValue NotMask = DAG.getNode(ISD::XOR, DL, MaskTy, Mask, AllOnes);
503 // Implement VSELECT in terms of XOR, AND, OR
513 // AND,OR,XOR, we will have to scalarize the op.
516 // This operation also isn't safe with AND, OR, XOR when the boolean
520 TLI.getOperationAction(ISD::XOR, V
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H A DTargetLowering.cpp1116 case ISD::XOR:
1122 if (Op.getOpcode() == ISD::XOR &&
1316 case ISD::XOR:
1364 // for XOR, we prefer to force bits to 1 if they will make a -1.
2168 if ((N0.getOpcode() == ISD::XOR ||
2170 N0.getOperand(0).getOpcode() == ISD::XOR &&
2182 if (N0.getOpcode() == ISD::XOR)
2186 N0.getOperand(0).getOpcode() == ISD::XOR);
2203 if ((Op0.getOpcode() == ISD::XOR) &&
2479 N0.getOpcode() == ISD::XOR) {
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H A DDAGCombiner.cpp1117 case ISD::XOR: return visitXOR(N);
1198 case ISD::XOR:
1640 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
1727 return CombineTo(N, DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0),
2305 // For each of OP in AND/OR/XOR:
3347 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C);
3350 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
3355 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1);
3383 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V,
3395 LHS = DAG.getNode(ISD::XOR, LH
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H A DFastISel.cpp351 // MVT::i1 is special. Allow AND, OR, or XOR because they
355 ISDOpcode == ISD::XOR))
882 unsigned IntResultReg = FastEmit_ri_(IntVT.getSimpleVT(), ISD::XOR,
980 return SelectBinaryOp(I, ISD::XOR);
H A DSelectionDAGBuilder.h488 void visitXor (const User &I) { visitBinary(I, ISD::XOR); }
H A DSelectionDAGDumper.cpp170 case ISD::XOR: return "xor";
/macosx-10.10/cxxfilt-11/cxxfilt/include/opcode/
H A Dm88k.h265 #define XOR ADD+7 macro
/macosx-10.10/vim-55/runtime/syntax/
H A Doccam.vim44 syn keyword occamOperator AFTER TIMES MINUS PLUS INITIAL REM AND OR XOR NOT
H A Dabap.vim113 syn keyword abapOperator EQ NE LT LE GT GE NOT AND OR XOR IN LIKE BETWEEN
H A Dplm.vim75 syn keyword plmReserved THEN TO WHILE WORD XOR
H A Dsdl.vim73 syn keyword sdlStatement SELECT SPELLING SUBSTRUCTURE XOR
H A Dtasm.vim64 syn keyword tasmInstruction VERW WBINVD WRMSR XADD XCHG XLAT XOR
H A Dmasm.vim70 syn keyword masmOperator AND NOT OR SHL SHR XOR MOD DUP
202 syn keyword masmOpcode XOR
/macosx-10.10/cxxfilt-11/cxxfilt/opcodes/
H A Dm88k-dis.c151 {0xf4005000,"xor ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,XOR ,0,1,1,1,0,0,0,0,0,0,0,0} },
152 {0xf4005400,"xor.c ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,XOR ,0,1,1,1,1,0,0,0,0,0,0,0} },
157 {0x50000000,"xor ",{21,5,REG} ,{16,5,REG} ,{0,16,HEX}, {1,1,PINT,XOR ,i16bit,1,0,1,0,0,0,0,0,0,0,0} },
158 {0x54000000,"xor.u ",{21,5,REG} ,{16,5,REG} ,{0,16,HEX}, {1,1,PINT,XOR ,i16bit,1,0,1,0,1,0,0,0,0,0,0} },
/macosx-10.10/llvmCore-3425.0.34/lib/Target/MBlaze/Disassembler/
H A DMBlazeDisassembler.cpp50 MBlaze::OR, MBlaze::AND, MBlaze::XOR, MBlaze::ANDN, //20,21,22,23
441 case 0x000: return MBlaze::XOR;
488 case MBlaze::XOR: return decodeXOR(insn);
/macosx-10.10/zsh-61/zsh/Src/
H A Dmath.c118 #define XOR 9 macro
180 * 10 XOR '^'
199 /* POSTMINUS UPLUS UMINUS AND XOR */
232 * 5 XOR '^'
255 /* POSTMINUS UPLUS UMINUS AND XOR */
642 return XOR;
1074 case XOR:
/macosx-10.10/llvmCore-3425.0.34/lib/Target/MSP430/
H A DMSP430ISelDAGToDAG.cpp466 case ISD::XOR:
/macosx-10.10/bash-94.1.2/bash-3.2/lib/termcap/grot/
H A Dconfigure782 #define XOR(e, f) (((e) && !(f)) || (!(e) && (f)))
784 if (XOR (islower (i), ISLOWER (i)) || toupper (i) != TOUPPER (i)) exit(2);
/macosx-10.10/llvmCore-3425.0.34/lib/Target/X86/
H A DX86ISelLowering.cpp812 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
813 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
814 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
815 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
924 setOperationAction(ISD::XOR, VT, Promote);
925 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1174 setOperationAction(ISD::XOR, VT, Promote);
1175 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1251 setTargetDAGCombine(ISD::XOR);
8272 DAG.getNode(ISD::XOR, d
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H A DX86ISelDAGToDAG.cpp316 case X86ISD::XOR:
323 case ISD::XOR: {
1514 XOR, enumerator in enum:AtomicOpc
1710 Op = XOR;
2089 case ISD::XOR: {
2111 // This only matters for OR and XOR, AND is unaffected.
2142 case ISD::XOR: Op = X86::XOR32ri8; break;
2153 case ISD::XOR: Op = CstVT==MVT::i8? X86::XOR64ri8 : X86::XOR64ri32; break;
H A DX86ISelLowering.h52 /// FXOR - Bitwise logical XOR of floating point values. This corresponds
253 INC, DEC, OR, XOR, AND, enumerator in enum:llvm::X86ISD::NodeType
/macosx-10.10/llvmCore-3425.0.34/lib/Target/PowerPC/
H A DPPCISelLowering.cpp333 setOperationAction(ISD::XOR , VT, Promote);
334 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
372 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
1365 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
4010 DAG.getNode(ISD::XOR, dl, MVT::i32,
4016 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
4241 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
4651 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
5189 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
5191 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
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