1/* Table of opcodes for the Motorola M88k family. 2 Copyright 1989, 1990, 1991, 1993, 2001, 2002 3 Free Software Foundation, Inc. 4 5This file is part of GDB and GAS. 6 7This program is free software; you can redistribute it and/or modify 8it under the terms of the GNU General Public License as published by 9the Free Software Foundation; either version 2 of the License, or 10(at your option) any later version. 11 12This program is distributed in the hope that it will be useful, 13but WITHOUT ANY WARRANTY; without even the implied warranty of 14MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15GNU General Public License for more details. 16 17You should have received a copy of the GNU General Public License 18along with this program; if not, write to the Free Software 19Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ 20 21/* 22 * Disassembler Instruction Table 23 * 24 * The first field of the table is the opcode field. If an opcode 25 * is specified which has any non-opcode bits on, a system error 26 * will occur when the system attempts the install it into the 27 * instruction table. The second parameter is a pointer to the 28 * instruction mnemonic. Each operand is specified by offset, width, 29 * and type. The offset is the bit number of the least significant 30 * bit of the operand with bit 0 being the least significant bit of 31 * the instruction. The width is the number of bits used to specify 32 * the operand. The type specifies the output format to be used for 33 * the operand. The valid formats are: register, register indirect, 34 * hex constant, and bit field specification. The last field is a 35 * pointer to the next instruction in the linked list. These pointers 36 * are initialized by init_disasm(). 37 * 38 * Revision History 39 * 40 * Revision 1.0 11/08/85 Creation date 41 * 1.1 02/05/86 Updated instruction mnemonic table MD 42 * 1.2 06/16/86 Updated SIM_FLAGS for floating point 43 * 1.3 09/20/86 Updated for new encoding 44 * 05/11/89 R. Trawick adapted from Motorola disassembler 45 */ 46 47#include <stdio.h> 48 49/* Define the number of bits in the primary opcode field of the instruction, 50 the destination field, the source 1 and source 2 fields. */ 51 52/* Size of opcode field. */ 53#define OP 8 54 55/* Size of destination. */ 56#define DEST 6 57 58/* Size of source1. */ 59#define SOURCE1 6 60 61/* Size of source2. */ 62#define SOURCE2 6 63 64/* Number of registers. */ 65#define REGs 32 66 67/* Type definitions. */ 68 69typedef unsigned int UINT; 70#define WORD long 71#define FLAG unsigned 72#define STATE short 73 74/* The next four equates define the priorities that the various classes 75 * of instructions have regarding writing results back into registers and 76 * signalling exceptions. */ 77 78/* PMEM is also defined in <sys/param.h> on Delta 88's. Sigh! */ 79#undef PMEM 80 81/* Integer priority. */ 82#define PINT 0 83 84/* Floating point priority. */ 85#define PFLT 1 86 87/* Memory priority. */ 88#define PMEM 2 89 90/* Not applicable, instruction doesn't write to regs. */ 91#define NA 3 92 93/* Highest of these priorities. */ 94#define HIPRI 3 95 96/* The instruction registers are an artificial mechanism to speed up 97 * simulator execution. In the real processor, an instruction register 98 * is 32 bits wide. In the simulator, the 32 bit instruction is kept in 99 * a structure field called rawop, and the instruction is partially decoded, 100 * and split into various fields and flags which make up the other fields 101 * of the structure. 102 * The partial decode is done when the instructions are initially loaded 103 * into simulator memory. The simulator code memory is not an array of 104 * 32 bit words, but is an array of instruction register structures. 105 * Yes this wastes memory, but it executes much quicker. 106 */ 107 108struct IR_FIELDS 109{ 110 unsigned op:OP, 111 dest: DEST, 112 src1: SOURCE1, 113 src2: SOURCE2; 114 int ltncy, 115 extime, 116 /* Writeback priority. */ 117 wb_pri; 118 /* Immediate size. */ 119 unsigned imm_flags:2, 120 /* Register source 1 used. */ 121 rs1_used:1, 122 /* Register source 2 used. */ 123 rs2_used:1, 124 /* Register source/dest. used. */ 125 rsd_used:1, 126 /* Complement. */ 127 c_flag:1, 128 /* Upper half word. */ 129 u_flag:1, 130 /* Execute next. */ 131 n_flag:1, 132 /* Uses writeback slot. */ 133 wb_flag:1, 134 /* Dest size. */ 135 dest_64:1, 136 /* Source 1 size. */ 137 s1_64:1, 138 /* Source 2 size. */ 139 s2_64:1, 140 scale_flag:1, 141 /* Scaled register. */ 142 brk_flg:1; 143}; 144 145struct mem_segs 146{ 147 /* Pointer (returned by calloc) to segment. */ 148 struct mem_wrd *seg; 149 150 /* Base load address from file headers. */ 151 unsigned long baseaddr; 152 153 /* Ending address of segment. */ 154 unsigned long endaddr; 155 156 /* Segment control flags (none defined). */ 157 int flags; 158}; 159 160#define MAXSEGS (10) /* max number of segment allowed */ 161#define MEMSEGSIZE (sizeof(struct mem_segs))/* size of mem_segs structure */ 162 163#if 0 164#define BRK_RD (0x01) /* break on memory read */ 165#define BRK_WR (0x02) /* break on memory write */ 166#define BRK_EXEC (0x04) /* break on execution */ 167#define BRK_CNT (0x08) /* break on terminal count */ 168#endif 169 170struct mem_wrd 171{ 172 /* Simulator instruction break down. */ 173 struct IR_FIELDS opcode; 174 union { 175 /* Memory element break down. */ 176 unsigned long l; 177 unsigned short s[2]; 178 unsigned char c[4]; 179 } mem; 180}; 181 182/* Size of each 32 bit memory model. */ 183#define MEMWRDSIZE (sizeof (struct mem_wrd)) 184 185extern struct mem_segs memory[]; 186extern struct PROCESSOR m78000; 187 188struct PROCESSOR 189{ 190 unsigned WORD 191 /* Execute instruction pointer. */ 192 ip, 193 /* Vector base register. */ 194 vbr, 195 /* Processor status register. */ 196 psr; 197 198 /* Source 1. */ 199 WORD S1bus, 200 /* Source 2. */ 201 S2bus, 202 /* Destination. */ 203 Dbus, 204 /* Data address bus. */ 205 DAbus, 206 ALU, 207 /* Data registers. */ 208 Regs[REGs], 209 /* Max clocks before reg is available. */ 210 time_left[REGs], 211 /* Writeback priority of reg. */ 212 wb_pri[REGs], 213 /* Integer unit control regs. */ 214 SFU0_regs[REGs], 215 /* Floating point control regs. */ 216 SFU1_regs[REGs], 217 Scoreboard[REGs], 218 Vbr; 219 unsigned WORD scoreboard, 220 Psw, 221 Tpsw; 222 /* Waiting for a jump instruction. */ 223 FLAG jump_pending:1; 224}; 225 226/* Size of immediate field. */ 227 228#define i26bit 1 229#define i16bit 2 230#define i10bit 3 231 232/* Definitions for fields in psr. */ 233 234#define psr_mode 31 235#define psr_rbo 30 236#define psr_ser 29 237#define psr_carry 28 238#define psr_sf7m 11 239#define psr_sf6m 10 240#define psr_sf5m 9 241#define psr_sf4m 8 242#define psr_sf3m 7 243#define psr_sf2m 6 244#define psr_sf1m 5 245#define psr_mam 4 246#define psr_inm 3 247#define psr_exm 2 248#define psr_trm 1 249#define psr_ovfm 0 250 251/* The 1 clock operations. */ 252 253#define ADDU 1 254#define ADDC 2 255#define ADDUC 3 256#define ADD 4 257 258#define SUBU ADD+1 259#define SUBB ADD+2 260#define SUBUB ADD+3 261#define SUB ADD+4 262 263#define AND_ ADD+5 264#define OR ADD+6 265#define XOR ADD+7 266#define CMP ADD+8 267 268/* Loads. */ 269 270#define LDAB CMP+1 271#define LDAH CMP+2 272#define LDA CMP+3 273#define LDAD CMP+4 274 275#define LDB LDAD+1 276#define LDH LDAD+2 277#define LD LDAD+3 278#define LDD LDAD+4 279#define LDBU LDAD+5 280#define LDHU LDAD+6 281 282/* Stores. */ 283 284#define STB LDHU+1 285#define STH LDHU+2 286#define ST LDHU+3 287#define STD LDHU+4 288 289/* Exchange. */ 290 291#define XMEMBU LDHU+5 292#define XMEM LDHU+6 293 294/* Branches. */ 295 296#define JSR STD+1 297#define BSR STD+2 298#define BR STD+3 299#define JMP STD+4 300#define BB1 STD+5 301#define BB0 STD+6 302#define RTN STD+7 303#define BCND STD+8 304 305/* Traps. */ 306 307#define TB1 BCND+1 308#define TB0 BCND+2 309#define TCND BCND+3 310#define RTE BCND+4 311#define TBND BCND+5 312 313/* Misc. */ 314 315#define MUL TBND + 1 316#define DIV MUL +2 317#define DIVU MUL +3 318#define MASK MUL +4 319#define FF0 MUL +5 320#define FF1 MUL +6 321#define CLR MUL +7 322#define SET MUL +8 323#define EXT MUL +9 324#define EXTU MUL +10 325#define MAK MUL +11 326#define ROT MUL +12 327 328/* Control register manipulations. */ 329 330#define LDCR ROT +1 331#define STCR ROT +2 332#define XCR ROT +3 333 334#define FLDCR ROT +4 335#define FSTCR ROT +5 336#define FXCR ROT +6 337 338#define NOP XCR +1 339 340/* Floating point instructions. */ 341 342#define FADD NOP +1 343#define FSUB NOP +2 344#define FMUL NOP +3 345#define FDIV NOP +4 346#define FSQRT NOP +5 347#define FCMP NOP +6 348#define FIP NOP +7 349#define FLT NOP +8 350#define INT NOP +9 351#define NINT NOP +10 352#define TRNC NOP +11 353#define FLDC NOP +12 354#define FSTC NOP +13 355#define FXC NOP +14 356 357#define UEXT(src,off,wid) \ 358 ((((unsigned int)(src)) >> (off)) & ((1 << (wid)) - 1)) 359 360#define SEXT(src,off,wid) \ 361 (((((int)(src))<<(32 - ((off) + (wid)))) >>(32 - (wid))) ) 362 363#define MAKE(src,off,wid) \ 364 ((((unsigned int)(src)) & ((1 << (wid)) - 1)) << (off)) 365 366#define opword(n) (unsigned long) (memaddr->mem.l) 367 368/* Constants and masks. */ 369 370#define SFU0 0x80000000 371#define SFU1 0x84000000 372#define SFU7 0x9c000000 373#define RRI10 0xf0000000 374#define RRR 0xf4000000 375#define SFUMASK 0xfc00ffe0 376#define RRRMASK 0xfc00ffe0 377#define RRI10MASK 0xfc00fc00 378#define DEFMASK 0xfc000000 379#define CTRL 0x0000f000 380#define CTRLMASK 0xfc00f800 381 382/* Operands types. */ 383 384enum operand_type 385{ 386 HEX = 1, 387 REG = 2, 388 CONT = 3, 389 IND = 3, 390 BF = 4, 391 /* Scaled register. */ 392 REGSC = 5, 393 /* Control register. */ 394 CRREG = 6, 395 /* Floating point control register. */ 396 FCRREG = 7, 397 PCREL = 8, 398 CONDMASK = 9, 399 /* Extended register. */ 400 XREG = 10, 401 /* Decimal. */ 402 DEC = 11 403}; 404 405/* Hashing specification. */ 406 407#define HASHVAL 79 408 409/* Structure templates. */ 410 411typedef struct 412{ 413 unsigned int offset; 414 unsigned int width; 415 enum operand_type type; 416} OPSPEC; 417 418struct SIM_FLAGS 419{ 420 int ltncy, /* latency (max number of clocks needed to execute). */ 421 extime, /* execution time (min number of clocks needed to execute). */ 422 wb_pri; /* writeback slot priority. */ 423 unsigned op:OP, /* simulator version of opcode. */ 424 imm_flags:2, /* 10,16 or 26 bit immediate flags. */ 425 rs1_used:1, /* register source 1 used. */ 426 rs2_used:1, /* register source 2 used. */ 427 rsd_used:1, /* register source/dest used. */ 428 c_flag:1, /* complement. */ 429 u_flag:1, /* upper half word. */ 430 n_flag:1, /* execute next. */ 431 wb_flag:1, /* uses writeback slot. */ 432 dest_64:1, /* double precision dest. */ 433 s1_64:1, /* double precision source 1. */ 434 s2_64:1, /* double precision source 2. */ 435 scale_flag:1; /* register is scaled. */ 436}; 437 438typedef struct INSTRUCTAB { 439 unsigned int opcode; 440 char *mnemonic; 441 OPSPEC op1,op2,op3; 442 struct SIM_FLAGS flgs; 443} INSTAB; 444 445 446#define NO_OPERAND {0,0,0} 447 448extern const INSTAB instructions[]; 449 450/* 451 * Local Variables: 452 * fill-column: 131 453 * End: 454 */ 455